| /freebsd-13-stable/sys/contrib/openzfs/module/zfs/ |
| H A D | vdev_raidz_math_avx2.c | 49 #define VR2(r...) VR2_(r, 1) macro
78 "vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
100 "vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
105 "vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
122 "vmovdqa %" VR2(r) ", %" VR6(r) "\n" \
127 "vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
142 "vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n" \
164 "vmovdqa %%" VR2(
[all...] |
| H A D | vdev_raidz_math_avx512bw.c | 53 #define VR2(r...) VR2_(r, 1) macro
81 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
103 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
108 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
125 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
130 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
145 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
167 "vmovdqa64 %%" VR2(
[all...] |
| H A D | vdev_raidz_math_powerpc_altivec_common.h | 56 #define VR2(r...) VR2_(r, 36) macro
152 "vxor " VR2(r) "," VR2(r) ",19\n" \
182 "vxor " VR2(r) "," VR2(r) ",19\n" \
214 "vxor " VR6(r) "," VR6(r) "," VR2(r) "\n" \
221 "vxor " VR2(r) "," VR2(r) "," VR0(r) "\n" \
238 "vxor " VR2(r) "," VR2(
[all...] |
| H A D | vdev_raidz_math_aarch64_neon_common.h | 55 #define VR2(r...) VR2_(r, 36) macro
151 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
181 "eor " VR2(r) ".16b," VR2(r) ".16b,v19.16b\n" \
213 "eor " VR6(r) ".16b," VR6(r) ".16b," VR2(r) ".16b\n" \
220 "eor " VR2(r) ".16b," VR2(r) ".16b," VR0(r) ".16b\n" \
237 "eor " VR2(r) ".16b," VR2(
[all...] |
| H A D | vdev_raidz_math_avx512f.c | 52 #define VR2(r...) VR2_(r, 1) macro
95 "vpxorq 0x80(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
109 "vpxorq %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
114 "vpxorq %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
131 "vmovdqa64 %" VR2(r) ", %" VR6(r) "\n" \
136 "vmovdqa64 %" VR0(r) ", %" VR2(r) "\n" \
149 "vmovdqa64 0x80(%[SRC]), %%" VR2(r) "\n" \
163 "vmovdqa64 %%" VR2(
[all...] |
| H A D | vdev_raidz_math_sse2.c | 51 #define VR2(r...) VR2_(r, 1, 2, 3, 4, 5, 6) macro
71 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
95 "pxor %" VR2(r) ", %" VR6(r) "\n" \
100 "pxor %" VR0(r) ", %" VR2(r) "\n" \
119 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
124 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
143 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
168 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
226 _MUL2_x2(VR2(r), VR3(r)); \
|
| H A D | vdev_raidz_math_ssse3.c | 50 #define VR2(r...) VR2_(r, 1) macro
79 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
101 "pxor %" VR2(r) ", %" VR6(r) "\n" \
106 "pxor %" VR0(r) ", %" VR2(r) "\n" \
123 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
128 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
143 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
165 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 224 bool operator() (unsigned VR1, unsigned VR2) const {
225 return operator[](VR1) < operator[](VR2);
299 bool operator() (unsigned VR1, unsigned VR2) const;
317 bool operator() (unsigned VR1, unsigned VR2) const;
328 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const {
338 if (VR1 == VR2)
341 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2);
352 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2];
355 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const {
356 if (VR1 == VR2)
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3067 Register VR2 = RegInfo.createVirtualRegister(RC); local
3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3080 .addReg(VR2)
|