Searched refs:TEGRA186_CLK_EQOS_AXI (Results 1 - 1 of 1) sorted by relevance

/freebsd-13-stable/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h270 * @def TEGRA186_CLK_EQOS_AXI
596 #define TEGRA186_CLK_EQOS_AXI 167 macro
797 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */

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