Searched refs:SubVec (Results 1 - 6 of 6) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6007 SDValue SubVec = Op.getOperand(1);
6012 if (SubVec.isUndef())
6033 SubVec, Idx);
6037 MVT SubVecVT = SubVec.getSimpleValueType();
6052 // Merge them together, SubVec should be zero extended.
6053 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
6055 SubVec, ZeroIdx);
6056 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
6060 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
6061 Undef, SubVec, ZeroId
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1156 SDValue SubVec = N->getOperand(1); local
1163 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
1175 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
1194 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr,
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| H A D | DAGCombiner.cpp | 17420 SDValue SubVec = InsertVal.getOperand(0);
17422 EVT SubVecVT = SubVec.getValueType();
17455 ConcatOps[0] = SubVec;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8647 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); local
8651 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt,
8657 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec,
14402 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, local
14405 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(),
18585 Value *SubVec = Builder.CreateExtractValue(VldN, Index); local
18589 SubVec = Builder.CreateIntToPtr(
18590 SubVec,
18593 SubVecs[SV].push_back(SubVec);
18602 auto &SubVec = SubVecs[SVI]; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9923 Value *SubVec = Builder.CreateExtractValue(LdN, Index); local
9927 SubVec = Builder.CreateIntToPtr(
9928 SubVec, FixedVectorType::get(SVI->getType()->getElementType(),
9930 SubVecs[SVI].push_back(SubVec);
9939 auto &SubVec = SubVecs[SVI]; local
9941 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0];
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5388 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
5391 Pieces.push_back(SubVec);
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