/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | BasicTTIImpl.h | 958 auto *SubVT = FixedVectorType::get(VT->getElementType(), NumSubElts); local 1038 thisT()->getVectorInstrCost(Instruction::InsertElement, SubVT, i); 1054 thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVT, i); 1067 SubVT = FixedVectorType::get(I8Type, NumSubElts); 1081 thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVT, i);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 2196 EVT SubVT = N->getValueType(0); local 2201 if (SubVT.isScalableVector() != 2212 assert(IdxVal + SubVT.getVectorMinNumElements() <= LoElts && 2214 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 2216 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 3944 EVT SubVT = Mask->getValueType(0); local 3945 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
|
H A D | SelectionDAG.cpp | 2745 EVT SubVT = N0.getValueType(); 2746 unsigned SubBitWidth = SubVT.getScalarSizeInBits(); 2749 if (!(SubVT.isInteger() || SubVT.isFloatingPoint())) 9340 EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts); 9341 if (!TLI->isExtractSubvectorCheap(SubVT, OpVT, 0)) 9344 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op,
|
H A D | DAGCombiner.cpp | 19111 static SDValue getSubVectorSrc(SDValue V, SDValue Index, EVT SubVT) { argument 19113 V.getOperand(1).getValueType() == SubVT && V.getOperand(2) == Index) { 19118 V.getOperand(0).getValueType() == SubVT && 19119 (IndexC->getZExtValue() % SubVT.getVectorNumElements()) == 0) { 19120 uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorNumElements(); 19140 EVT SubVT = Extract->getValueType(0); local 19141 if (!TLI.isOperationLegalOrCustom(BinOpcode, SubVT)) 19144 SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT); 19145 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); 19156 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub 20455 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), local [all...] |
H A D | TargetLowering.cpp | 1094 EVT SubVT = Op.getOperand(0).getValueType(); local 1096 unsigned NumSubElts = SubVT.getVectorNumElements(); 2490 EVT SubVT = Op.getOperand(0).getValueType(); local 2492 unsigned NumSubElts = SubVT.getVectorNumElements();
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 2789 EVT SubVT = ShiftAmt->getValueType(0); local 2790 if (SubVT == MVT::i32) { 2794 assert(SubVT == MVT::i64); 2799 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); 2801 CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 5862 EVT SubVT = Sub.getValueType(); 5865 if (VT.getSizeInBits() == (SubVT.getSizeInBits() * 2) && 5869 Src.getOperand(1).getValueType() == SubVT && 6165 EVT SubVT = V1.getValueType(); 6166 EVT SubSVT = SubVT.getScalarType(); 6167 unsigned SubNumElts = SubVT.getVectorNumElements(); 6168 unsigned SubVectorWidth = SubVT.getSizeInBits(); 7459 EVT SubVT = Sub.getValueType(); 7460 unsigned NumSubElts = SubVT.getVectorNumElements(); 7484 if (llvm::any_of(SubInputs, [SubVT](SDValu [all...] |
H A D | X86ISelDAGToDAG.cpp | 3768 EVT SubVT = ShiftAmt.getValueType(); local 3769 SDValue Zero = CurDAG->getConstant(0, DL, SubVT); 3770 SDValue Neg = CurDAG->getNode(ISD::SUB, DL, SubVT, Zero, Add1);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | LoopVectorize.cpp | 2319 auto *SubVT = FixedVectorType::get(ScalarTy, VF); 2337 if (StoredVec->getType() != SubVT) 2338 StoredVec = createBitOrPointerCast(StoredVec, SubVT, DL);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 8356 EVT SubVT = SubV1.getValueType(); local 8364 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) { 8369 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT), 8646 EVT SubVT = MVT::getVectorVT(ElType, NumElts); local 8647 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); 8651 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt,
|