/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.h | 96 // SrcReg2 if having two register operands, and the value it compares against 99 Register &SrcReg2, int &CmpMask, 106 Register SrcReg2, int CmpMask, int CmpValue,
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H A D | LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask, 186 SrcReg2 = Register(); 192 SrcReg2 = MI.getOperand(1).getReg(); 206 unsigned SrcReg2, int ImmValue, 211 OI->getOperand(2).getReg() == SrcReg2) || 212 (OI->getOperand(1).getReg() == SrcReg2 && 284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, 304 if (SrcReg2 != 0) 330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 382 if (SrcReg2 ! 177 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &CmpMask, int &CmpValue) const argument 205 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument 283 optimizeCompareInstr( MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int , int CmpValue, const MachineRegisterInfo *MRI) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 627 // SrcReg2 is the register if the source operand is a register, 631 Register SrcReg2 = local 636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) 684 // Clear any intervening kills of SrcReg and SrcReg2. 688 if (SrcReg2) 689 MBBI->clearRegisterKills(SrcReg2, TRI);
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H A D | SystemZInstrInfo.h | 237 Register &SrcReg2, int &Mask, int &Value) const override;
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H A D | SystemZInstrInfo.cpp | 517 Register &SrcReg2, int &Mask, 524 SrcReg2 = 0; 516 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 859 unsigned SrcReg2 = 0; local 861 SrcReg2 = getRegForValue(SrcValue2); 862 if (SrcReg2 == 0) 870 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; 893 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); 943 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 945 SrcReg2 = ExtReg; 951 .addReg(SrcReg1).addReg(SrcReg2); 1362 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); local [all...] |
H A D | PPCInstrInfo.h | 485 Register &SrcReg2, int &Mask, int &Value) const override; 488 Register SrcReg2, int Mask, int Value,
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H A D | PPCInstrInfo.cpp | 1824 Register &SrcReg2, int &Mask, 1835 SrcReg2 = 0; 1846 SrcReg2 = MI.getOperand(2).getReg(); 1854 Register SrcReg2, int Mask, int Value, 1960 if (SrcReg2 != 0) 2035 Instr.getOperand(2).getReg() == SrcReg2) || 2036 (Instr.getOperand(1).getReg() == SrcReg2 && 2082 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 4506 Register SrcReg2 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 213 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 216 Register &SrcReg2, int &CmpMask, 221 Register SrcReg2, int CmpMask, int CmpValue,
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H A D | AArch64SIMDInstrOpt.cpp | 439 Register SrcReg2 = MI.getOperand(3).getReg(); local 445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { 448 .addReg(SrcReg2, Src2IsKill)
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H A D | AArch64InstrInfo.cpp | 1026 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 1029 Register &SrcReg2, int &CmpMask, 1054 SrcReg2 = MI.getOperand(2).getReg(); 1063 SrcReg2 = 0; 1073 SrcReg2 = 0; 1223 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, 1253 if (CmpValue != 0 || SrcReg2 != 0) 4416 unsigned SrcReg2; 4420 SrcReg2 = *ReplacedAddend; 4423 SrcReg2 1222 optimizeCompareInstr( MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 497 /// in SrcReg and SrcReg2 if having two register operands, and the value it 501 Register &SrcReg2, int &CmpMask, 508 Register SrcReg2, int CmpMask, int CmpValue,
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H A D | X86InstrInfo.cpp | 1537 Register SrcReg2; local 1540 SrcReg2, isKill2, ImplicitOp2, LV)) 1549 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 1551 LV->replaceKillInstruction(SrcReg2, MI, *NewMI); 3756 Register &SrcReg2, int &CmpMask, 3768 SrcReg2 = 0; 3782 SrcReg2 = 0; 3791 SrcReg2 = MI.getOperand(2).getReg(); 3803 SrcReg2 = 0; 3816 SrcReg2 3755 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &CmpMask, int &CmpValue) const argument 3842 isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, Register SrcReg2, int ImmMask, int ImmValue, const MachineInstr &OI) argument 4032 optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1415 unsigned SrcReg2 = 0; local 1417 SrcReg2 = getRegForValue(Src2Value); 1418 if (SrcReg2 == 0) return false; 1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); 1427 if (SrcReg2 == 0) return false; 1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); 1436 .addReg(SrcReg1).addReg(SrcReg2)); 1763 unsigned SrcReg2 local [all...] |
H A D | ARMBaseInstrInfo.cpp | 2731 /// in SrcReg and SrcReg2 if having two register operands, and the value it 2735 Register &SrcReg2, int &CmpMask, 2743 SrcReg2 = 0; 2751 SrcReg2 = MI.getOperand(1).getReg(); 2758 SrcReg2 = 0; 2806 Register SrcReg, Register SrcReg2, 2812 OI->getOperand(2).getReg() == SrcReg2) || 2813 (OI->getOperand(1).getReg() == SrcReg2 && 2821 OI->getOperand(3).getReg() == SrcReg2) || 2822 (OI->getOperand(2).getReg() == SrcReg2 2734 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &CmpMask, int &CmpValue) const argument 2805 isRedundantFlagInstr(const MachineInstr *CmpI, Register SrcReg, Register SrcReg2, int ImmValue, const MachineInstr *OI, bool &IsThumb1) argument 2941 optimizeCompareInstr( MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument 3229 Register SrcReg, SrcReg2; local [all...] |
H A D | ARMBaseInstrInfo.h | 299 /// in SrcReg and SrcReg2 if having two register operands, and the value it 303 Register &SrcReg2, int &CmpMask, 311 Register SrcReg2, int CmpMask, int CmpValue,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | PeepholeOptimizer.cpp | 610 Register SrcReg, SrcReg2; local 612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 613 SrcReg.isPhysical() || SrcReg2.isPhysical()) 618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 269 /// in SrcReg and SrcReg2 if having two register operands, and the value it 273 Register &SrcReg2, int &Mask, int &Value) const override;
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H A D | HexagonInstrInfo.cpp | 1789 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it 1793 Register &SrcReg2, int &Mask, 1854 SrcReg2 = MI.getOperand(2).getReg(); 1869 SrcReg2 = 0; 1792 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1418 /// in SrcReg and SrcReg2 if having two register operands, and the value it 1422 Register &SrcReg2, int &Mask, int &Value) const { 1430 Register SrcReg2, int Mask, int Value, 1421 analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const argument 1429 optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
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