| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPostRewrite.cpp | 112 Register Src2Reg = MBBI->getOperand(2).getReg(); local
115 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
120 if (DestReg != Src1Reg && DestReg != Src2Reg) {
133 Src2Reg = DestReg;
139 if (DestReg != Src1Reg && DestReg == Src2Reg) {
141 std::swap(Src1Reg, Src2Reg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
323 Src2Reg = MCI.getOperand(2).getReg();
325 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
331 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
339 Src2Reg = MCI.getOperand(2).getReg();
341 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
358 Src2Reg = MCI.getOperand(2).getReg();
360 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
368 Src2Reg = MCI.getOperand(2).getReg();
369 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg)
[all...] |
| H A D | HexagonMCCompound.cpp | 80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
98 Src2Reg = MI.getOperand(2).getReg();
101 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg))
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 276 Register Src2Reg = MI->getOperand(3).getReg(); local
292 .addReg(Src2Reg, getKillRegState(Src2Kill));
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1202 Register Src2Reg = MI.getOperand(2).getReg(); local
1205 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1206 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1226 Register Src2Reg = MI.getOperand(2).getReg(); local
1230 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1231 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
3325 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
3341 Src2Reg = MI.getOperand(2).getReg();
3344 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3815 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2290 unsigned Src2Reg = Inst.getOperand(1).getReg(); local
2291 if (DestReg == Src2Reg)
2296 if (DestReg + 1 == Src2Reg)
2323 unsigned Src2Reg = Inst.getOperand(1).getReg(); local
2324 if (DestReg == Src2Reg)
2327 // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
2328 if (DestReg == Src2Reg + 1)
2332 unsigned Src2Reg = Inst.getOperand(1).getReg(); local
2333 if (DestReg == Src2Reg)
2338 if (DestReg + 1 == Src2Reg)
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1428 Register Src2Reg = I.getOperand(2).getReg(); local
1435 Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI);
1454 Shl.addUse(Src2Reg);
1466 Register Src2Reg = I.getOperand(2).getReg(); local
1496 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
3085 Register Src2Reg = I.getOperand(3).getReg(); local
3234 std::swap(SrcReg, Src2Reg);
3237 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
3297 Register Src2Reg = I.getOperand(2).getReg(); local
3304 Src2Reg, /* LaneId
4302 Register Src2Reg = I.getOperand(2).getReg(); local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1046 unsigned Src2Reg = getRegForValue(SI->getFalseValue()); local
1049 if (!Src1Reg || !Src2Reg || !CondReg)
1065 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2692 unsigned Src2Reg = getRegForValue(Src2Val); local
2693 if (!Src2Reg)
2702 Src1IsKill, Src2Reg, Src2IsKill);
2820 unsigned Src2Reg = getRegForValue(SI->getFalseValue()); local
2823 if (!Src1Reg || !Src2Reg)
2827 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2831 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
|