Searched refs:Src1 (Results 1 - 25 of 43) sorted by relevance

12

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DConstantFoldingMIRBuilder.h51 const SrcOp &Src1 = SrcOps[1]; variable
53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
62 const SrcOp &Src1 = SrcOps[1]; variable
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
H A DMachineIRBuilder.h1337 const SrcOp &Src1,
1339 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1354 const SrcOp &Src1,
1356 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1370 const SrcOp &Src1,
1372 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1376 const SrcOp &Src1,
1378 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1382 const SrcOp &Src1,
1384 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flag
1336 buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1353 buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1369 buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1375 buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1381 buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1387 buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1393 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1399 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1405 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1411 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1417 buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1423 buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1429 buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1446 buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1461 buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1467 buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1511 buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1518 buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional<unsigned> Flags = None) argument
1525 buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional<unsigned> Flags = None) argument
1532 buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional<unsigned> Flags = None) argument
1587 buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1613 buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1619 buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1625 buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
1631 buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1
192 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
206 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
220 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp161 Register Src1 = local
165 (void) Src1;
167 (TRI.getEncodingValue(Src1) & 0xff) < 127)
168 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
212 unsigned Src1 = 0; local
218 Src1 = MI.getOperand(Src1Idx).getReg();
224 Src1 = TRI.getSubReg(Src1, SubRegIndex);
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...]
H A DSIOptimizeExecMasking.cpp110 const MachineOperand &Src1 = MI.getOperand(1); local
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
126 const MachineOperand &Src1 = MI.getOperand(1); local
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
390 MachineOperand &Src1 = SaveExecInst->getOperand(2); local
395 OtherOp = &Src1;
396 } else if (Src1.isReg() && Src1
[all...]
H A DGCNDPPCombine.cpp237 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
238 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
243 DPPInst.add(*Src1);
330 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); local
331 if (!Src1 || !Src1->isReg()) {
339 CombOldVGPR = getRegSubRegPair(*Src1);
517 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); local
518 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
523 assert(Src0 && "Src1 withou
[all...]
H A DSIPeepholeSDWA.cpp571 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
573 if (Register::isPhysicalRegister(Src1->getReg()) ||
580 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
583 Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
609 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
612 if (Register::isPhysicalRegister(Src1->getReg()) ||
618 return std::make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD);
621 Src1, Dst, BYTE_1, false, false,
644 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
645 auto Offset = foldToImm(*Src1);
691 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
1050 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
[all...]
H A DSIShrinkInstructions.cpp193 const MachineOperand &Src1 = MI.getOperand(1); local
194 if (!Src1.isImm())
205 if (isKImmOrKUImmOperand(TII, Src1, HasUImm)) {
219 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) ||
220 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) {
327 MachineOperand *Src1 = &MI.getOperand(2); local
329 MachineOperand *SrcImm = Src1;
645 MachineOperand *Src1 = &MI.getOperand(2); local
647 if (!Src0->isReg() && Src1->isReg()) {
649 std::swap(Src0, Src1);
[all...]
H A DSIFoldOperands.cpp1030 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx)); local
1032 if (!Src0->isImm() && !Src1->isImm())
1057 if (Src0->isImm() && Src1->isImm()) {
1059 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1076 if (Src0->isImm() && !Src1->isImm()) {
1077 std::swap(Src0, Src1);
1081 int32_t Src1Val = static_cast<int32_t>(Src1->getImm());
1140 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); local
1143 if (Src1->isIdenticalTo(*Src0) &&
1306 const MachineOperand *Src1 local
1422 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
1451 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
[all...]
H A DSIInstrInfo.cpp1830 MachineOperand &Src1,
1894 MachineOperand &Src1 = MI.getOperand(Src1Idx); local
1897 if (Src0.isReg() && Src1.isReg()) {
1904 } else if (Src0.isReg() && !Src1.isReg()) {
1907 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1908 } else if (!Src0.isReg() && Src1.isReg()) {
1910 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1918 Src1, AMDGPU::OpName::src1_modifiers);
2618 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); local
2624 if (!Src1
1827 swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const argument
2908 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); local
3311 const MachineOperand *Src1 local
3332 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); local
3387 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); local
3831 const MachineOperand &Src1 = MI.getOperand(Src1Idx); local
3844 const MachineOperand &Src1 = MI.getOperand(Src1Idx); local
4359 MachineOperand &Src1 = MI.getOperand(Src1Idx); local
4475 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]); local
5376 MachineOperand &Src1 = Inst.getOperand(3); local
5554 MachineOperand &Src1 = Inst.getOperand(2); local
5652 MachineOperand &Src1 = Inst.getOperand(2); local
5718 MachineOperand &Src1 = Inst.getOperand(2); local
5747 MachineOperand &Src1 = Inst.getOperand(2); local
5838 MachineOperand &Src1 = Inst.getOperand(2); local
5900 MachineOperand &Src1 = Inst.getOperand(2); local
5964 MachineOperand &Src1 = Inst.getOperand(2); local
6138 MachineOperand &Src1 = Inst.getOperand(2); local
[all...]
H A DSIFixSGPRCopies.cpp710 MachineOperand &Src1 = MI.getOperand(Src1Idx);
715 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
716 Src1.getReg() != AMDGPU::M0)) {
723 for (MachineOperand *MO : {&Src0, &Src1}) {
748 .add(Src1);
749 Src1.ChangeToRegister(AMDGPU::M0, false);
H A DSILoadStoreOptimizer.cpp1421 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); local
1426 .add(*Src1)
1584 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); local
1589 .add(*Src1)
1760 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); local
1764 BaseLo = *Src1;
1766 if (!(Offset0P = extractConstOffset(*Src1)))
1772 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);
1775 std::swap(Src0, Src1);
1777 if (!Src1
[all...]
H A DSIISelLowering.cpp3756 MachineOperand &Src1 = MI.getOperand(3); local
3761 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3780 MachineOperand &Src1 = MI.getOperand(2); local
3791 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3793 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
3828 MachineOperand &Src1 = MI.getOperand(2); local
3833 const TargetRegisterClass *Src1RC = Src1.isReg()
3834 ? MRI.getRegClass(Src1.getReg())
3845 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
3850 MI, MRI, Src1, Src1R
3891 MachineOperand &Src1 = MI.getOperand(3); local
4044 Register Src1 = MI.getOperand(2).getReg(); local
4610 SDValue Src1 = N->getOperand(2); local
4686 SDValue Src1 = N->getOperand(2); local
4698 SDValue Src1 = N->getOperand(2); local
7273 SDValue Src1 = Op.getOperand(5); local
8098 SDValue Src1 = Op.getOperand(1); local
9720 SDValue Src1 = N->getOperand(1); local
9757 SDValue Src1 = N->getOperand(1); local
10890 SDValue Src1 = Node->getOperand(1); local
[all...]
H A DAMDGPURegisterBankInfo.cpp1357 Register Src1 = getSrcRegIgnoringCopies(*MRI, Add->getOperand(2).getReg()); local
1360 const RegisterBank *Src1Bank = RBI.getRegBank(Src1, *MRI, *RBI.TRI);
1364 SOffsetReg = Src1;
1369 VOffsetReg = Src1;
1622 Register Src1) {
1624 auto Cmp = B.buildICmp(Pred, CmpType, Src0, Src1);
1625 return B.buildSelect(Dst, Cmp, Src0, Src1);
1633 Register Src1 = MI.getOperand(2).getReg(); local
1636 MachineInstr *Sel = buildExpandedScalarMinMax(B, Pred, Dst, Src0, Src1);
2427 Register Src1 local
1619 buildExpandedScalarMinMax(MachineIRBuilder &B, CmpInst::Predicate Pred, Register Dst, Register Src0, Register Src1) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp145 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
148 SDValue Src1, SDValue Src2, uint64_t Size) {
150 EVT PtrVT = Src1.getValueType();
160 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
163 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
182 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
189 SDValue CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
233 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
236 SDVTList VTs = DAG.getVTList(Src1
147 emitCLC(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
181 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
232 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
[all...]
H A DSystemZSelectionDAGInfo.h41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; local
328 Src1 = MOSrc1->getReg();
347 if (!Src1) {
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp134 unsigned getMuxOpcode(const MachineOperand &Src1,
208 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, argument
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); local
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
323 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
324 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
H A DHexagonPeephole.cpp156 MachineOperand &Src1 = MI.getOperand(1); local
158 if (Src1.getImm() != 0)
173 MachineOperand &Src1 = MI.getOperand(1); local
178 Register SrcReg = Src1.getReg();
H A DHexagonConstPropagation.cpp1301 // X <= 0 and Src1 < 0 => cannot compare
1874 bool evaluateHexCompare2(uint32_t Cmp, const MachineOperand &Src1,
2574 // Classic compare: Dst0 = CMP Src1, Src2
2583 const MachineOperand &Src1 = MI.getOperand(1); local
2588 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result);
2606 const MachineOperand &Src1, const MachineOperand &Src2,
2609 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2610 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm();
2612 RegisterSubReg R1(Src1);
2621 APInt A1 = getCmpImm(Opc, 1, Src1);
2605 evaluateHexCompare2(unsigned Opc, const MachineOperand &Src1, const MachineOperand &Src2, const CellMap &Inputs, bool &Result) argument
2640 const MachineOperand &Src1 = MI.getOperand(1); local
3034 const MachineOperand &Src1 = MI.getOperand(1); local
[all...]
/freebsd-13-stable/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h54 If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned.
55 If Src1 is non-NULL and Src2 is NULL, then a duplicate of Src1 is returned.
56 If Src1 and Src2 are both NULL, then a copy of an end-of-device-path is returned.
58 @param Src1 Points to the first device path.
68 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1443 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, argument
1445 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2);
1450 return maxnum(Src1, Src2);
1452 APFloat::cmpResult Cmp1 = Max3.compare(Src1);
1457 return maxnum(Src0, Src1);
2356 Value *Src1 = II->getArgOperand(1); local
2358 if (match(Src0, m_FNeg(m_Value(X))) && match(Src1, m_FNeg(m_Value(Y)))) {
2366 match(Src1, m_FAbs(m_Specific(X)))) {
2388 return BinaryOperator::CreateFMulFMF(Src0, Src1, II);
3593 Value *Src1 local
3670 Value *Src1 = II->getArgOperand(1); local
3698 Value *Src1 = II->getArgOperand(1); local
3793 Value *Src1 = II->getArgOperand(1); local
3866 Value *Src1 = II->getArgOperand(1); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DInferAddressSpaces.cpp634 Constant *Src1 = CE->getOperand(2); local
636 Src1->getType()->getPointerAddressSpace()) {
640 ConstantExpr::getAddrSpaceCast(Src1, TargetType));
824 Value *Src1 = Op.getOperand(2); local
830 auto J = InferredAddrSpace.find(Src1);
832 J->second : Src1->getType()->getPointerAddressSpace();
835 auto *C1 = dyn_cast<Constant>(Src1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEMIRBuilder.cpp170 const SrcOp &Src1 = SrcOps[1];
172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
H A DLegalizerHelper.cpp1335 Register Src1 = MI.getOperand(1).getReg();
1336 LLT SrcTy = MRI.getType(Src1);
1348 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
3890 Register Src1 = MI.getOperand(1).getReg(); local
3897 unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3910 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
4818 Register Src1 = MI.getOperand(2).getReg(); local
4823 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4824 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4834 Register Src1 local
4885 Register Src1 = MI.getOperand(2).getReg(); local
[all...]

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