Searched refs:SelectCC (Results 1 - 3 of 3) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1874 SDValue SelectCC = FNeg.getOperand(0); local
1875 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1876 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1877 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1878 !isHWTrueValue(SelectCC.getOperand(2)) ||
1879 !isHWFalseValue(SelectCC.getOperand(3))) {
1884 SelectCC.getOperand(0), // LHS
1885 SelectCC.getOperand(1), // RHS
1888 SelectCC.getOperand(4)); // CC
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 218 /// SelectCC - Select a comparison of the specified values with the
220 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3708 /// SelectCC - Select a comparison of the specified values with the specified
3710 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, function in class:PPCDAGToDAGISel
4172 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
4176 // The correct compare instruction is already set by SelectCC()
5007 // Make use of SelectCC to generate the comparison to set CR bits, for
5008 // equality comparisons having one literal operand, SelectCC probably
5014 SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl);
5040 SDValue CCReg = SelectCC(
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4719 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); local
4722 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
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