/freebsd-13-stable/contrib/elftoolchain/libdwarf/ |
H A D | dwarf_seterror.c | 37 #define SET_FIELD(D, R, F) \ macro 50 SET_FIELD(dbg, oldhandler, errhand); 60 SET_FIELD(dbg, oldarg, errarg);
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/freebsd-13-stable/sys/dev/qlnx/qlnxe/ |
H A D | ecore_roce.c | 439 SET_FIELD(p_ramrod->flags, 443 SET_FIELD(p_ramrod->flags, 447 SET_FIELD(p_ramrod->flags, 451 SET_FIELD(p_ramrod->flags, 455 SET_FIELD(p_ramrod->flags, 459 SET_FIELD(p_ramrod->flags, 463 SET_FIELD(p_ramrod->flags, 467 SET_FIELD(p_ramrod->flags, 475 SET_FIELD(p_ramrod->flags, 608 SET_FIELD(p_ramro [all...] |
H A D | ecore_init_fw_funcs.c | 173 #define QM_CMD_SET_FIELD(var, cmd, field, value) SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value) 175 #define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, vp_pq_id, rl_id, ext_voq, wrr) OSAL_MEMSET(&map, 0, sizeof(map)); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_VALID, rl_valid); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, vp_pq_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_ID, rl_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VOQ, ext_voq); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, wrr); STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, *((u32 *)&map)) 1506 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1); 1509 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID_MASK, GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK); 1510 SET_FIELD(cam_lin [all...] |
H A D | ecore_cxt.c | 1501 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1502 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1503 SET_FIELD(cdu_params, (u32)CDUC_NCIB, elems_per_page); 1514 SET_FIELD(cdu_params, (u32)CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1515 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1516 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1526 SET_FIELD(cdu_params, (u32)CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1527 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1528 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1578 SET_FIELD(cdu_seg_param [all...] |
H A D | ecore_hw.c | 392 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 393 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 398 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 399 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 400 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 419 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 420 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 421 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 435 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 436 SET_FIELD(contro [all...] |
H A D | ecore_rdma.c | 700 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_RNR_NAK, 1); 701 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 702 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 703 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_RESIZE_CQ, 1); 704 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 705 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 706 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_ZBVA, 1); 707 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 716 SET_FIELD(dev->dev_caps, ECORE_RDMA_DEV_CAP_ATOMIC_OP, 1); 1686 SET_FIELD(q [all...] |
H A D | ecore_int.c | 1451 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1452 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1453 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1454 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1455 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1474 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1482 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1484 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1485 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1503 SET_FIELD(pi_entr [all...] |
H A D | ecore_l2.c | 415 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 416 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 421 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE, 424 SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL, 427 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR, 430 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS, 433 SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG, 436 SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION, 439 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME, 531 SET_FIELD(capabilitie [all...] |
H A D | ecore_ll2.c | 705 SET_FIELD(bd_flags, CORE_TX_BD_DATA_FORCE_VLAN_MODE, 1); 706 SET_FIELD(bd_flags, CORE_TX_BD_DATA_L4_PROTOCOL, 1); 1382 SET_FIELD(action_on_error, 1386 SET_FIELD(action_on_error, 1496 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_DEST, DB_DEST_XCM); 1497 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_AGG_CMD, 1499 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_AGG_VAL_SEL, 1702 SET_FIELD(start_bd->bitfield1, CORE_TX_BD_L4_HDR_OFFSET_W, 1704 SET_FIELD(start_bd->bitfield1, CORE_TX_BD_TX_DST, tx_dest); 1706 SET_FIELD(bd_dat [all...] |
H A D | ecore_spq.c | 291 SET_FIELD(p_cxt->xstorm_ag_context.flags10, 293 SET_FIELD(p_cxt->xstorm_ag_context.flags1, 295 /*SET_FIELD(p_cxt->xstorm_ag_context.flags10, 297 SET_FIELD(p_cxt->xstorm_ag_context.flags9, 628 SET_FIELD(p_db_data->params, CORE_DB_DATA_DEST, DB_DEST_XCM); 629 SET_FIELD(p_db_data->params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_MAX); 630 SET_FIELD(p_db_data->params, CORE_DB_DATA_AGG_VAL_SEL,
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H A D | ecore_iwarp.c | 302 SET_FIELD(p_ramrod->flags, 306 SET_FIELD(p_ramrod->flags, 310 SET_FIELD(p_ramrod->flags, 314 SET_FIELD(p_ramrod->flags, 318 SET_FIELD(p_ramrod->flags, 322 SET_FIELD(p_ramrod->flags, 386 SET_FIELD(p_ramrod->flags, IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN, 825 SET_FIELD(p_tcp_ramrod->tcp.flags, 829 SET_FIELD(p_tcp_ramrod->tcp.flags, 969 SET_FIELD(p_mpa_ramro [all...] |
H A D | ecore_dbg_fw_funcs.c | 4229 SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); 4230 SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, reg_id); 4280 SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, rule->num_cond_regs + reg_id); 4980 SET_FIELD(dev_data->bus.blocks[BLOCK_DBG].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, 0x1); 5143 SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, enable_mask); 5144 SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT, right_shift); 5145 SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK, force_valid_mask); 5146 SET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK, force_frame_mask); 5212 SET_FIELD(dev_data->bus.blocks[BLOCK_DBG].data, DBG_BUS_BLOCK_DATA_ENABLE_MASK, 0x1); 5408 SET_FIELD(bu [all...] |
H A D | ecore_sriov.c | 922 SET_FIELD(igu_vf_conf, IGU_VF_CONF_PARENT, p_hwfn->rel_pf_id); 995 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, vf->abs_vf_id); 996 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 1); 997 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, 0); 1003 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, qid); 1053 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
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H A D | ecore.h | 111 #define SET_FIELD(value, name, flag) \ macro
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H A D | ecore_dev.c | 921 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); 974 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); 6462 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 6463 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
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H A D | qlnx_os.c | 6862 SET_FIELD(txq->tx_db.data.params, 6864 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, 6866 SET_FIELD(txq->tx_db.data.params,
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/freebsd-13-stable/sys/dev/qlnx/qlnxr/ |
H A D | qlnxr_verbs.c | 3585 SET_FIELD(qp_params.modify_flags, 3595 SET_FIELD(qp_params.modify_flags, 3612 SET_FIELD(qp_params.modify_flags, 3647 SET_FIELD(qp_params.modify_flags, 3695 SET_FIELD(qp_params.modify_flags, \ 3717 SET_FIELD(qp_params.modify_flags,\ 3723 SET_FIELD(qp_params.modify_flags, 3730 SET_FIELD(qp_params.modify_flags, 3747 SET_FIELD(qp_params.modify_flags, 3754 SET_FIELD(qp_param [all...] |