Searched refs:Rsrc (Results 1 - 4 of 4) sorted by relevance
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 5126 // unique value of \p Rsrc across all lanes. In the best case we execute 1 5131 const DebugLoc &DL, MachineOperand &Rsrc) { 5149 Register VRsrc = Rsrc.getReg(); 5150 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); 5152 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI); 5204 // Build scalar Rsrc. 5212 // Update Rsrc operand to use the SGPR Rsrc. 5213 Rsrc.setReg(SRsrc); 5214 Rsrc 5129 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, MachineOperand &Rsrc) argument 5238 loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc, MachineDominatorTree *MDT, MachineBasicBlock::iterator Begin = nullptr, MachineBasicBlock::iterator End = nullptr) argument 5320 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) argument 5548 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx); local [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 1520 SDValue Addr, SDValue &Rsrc, 1528 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); 1630 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | local 1637 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); 1519 SelectMUBUFScratchOffen(SDNode *Parent, SDValue Addr, SDValue &Rsrc, SDValue &VAddr, SDValue &SOffset, SDValue &ImmOffset) const argument
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H A D | SIISelLowering.h | 70 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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H A D | SIISelLowering.cpp | 6307 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, argument 6324 Rsrc, 6362 Rsrc, // rsrc
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