/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | RDFRegisters.h | 71 struct RegisterRef { struct in namespace:llvm::rdf 75 RegisterRef() = default; 76 explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) function in struct:llvm::rdf::RegisterRef 83 bool operator== (const RegisterRef &RR) const { 87 bool operator!= (const RegisterRef &RR) const { 91 bool operator< (const RegisterRef &RR) const { 113 RegisterRef normalize(RegisterRef RR) const; 115 bool alias(RegisterRef RA, RegisterRef R [all...] |
H A D | RDFLiveness.h | 58 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA, 66 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA) { 70 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA, 73 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA) { 77 std::pair<NodeSet,bool> getAllReachingDefsRec(RegisterRef RefRR, 80 NodeAddr<RefNode*> getNearestAliasedRef(RegisterRef RefRR, 140 std::pair<NodeSet,bool> getAllReachingDefsRecImpl(RegisterRef RefRR,
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H A D | RDFGraph.h | 412 using RegisterSet = std::set<RegisterRef>; 518 RegisterRef getRegRef(const DataFlowGraph &G) const; 525 void setRegRef(RegisterRef RR, DataFlowGraph &G); 553 NodeAddr<RefNode*> getNextRef(RegisterRef RR, Predicate P, bool NextOnly, 740 PackedRegisterRef pack(RegisterRef RR) { 743 PackedRegisterRef pack(RegisterRef RR) const { 746 RegisterRef unpack(PackedRegisterRef PR) const { 747 return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); 750 RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const; 751 RegisterRef makeRegRe [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RDFRegisters.cpp | 97 RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { 115 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) 125 if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) 131 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { 162 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef R [all...] |
H A D | RDFLiveness.cpp | 106 NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, 145 RegisterRef RR = TA.Addr->getRegRef(DFG); 237 RegisterRef QR = DA.Addr->getRegRef(DFG); 269 Liveness::getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, 275 Liveness::getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode*> RefA, 322 NodeAddr<RefNode*> Liveness::getNearestAliasedRef(RegisterRef RefRR, 379 NodeSet Liveness::getAllReachedUses(RegisterRef RefRR, 395 RegisterRef UR = UA.Addr->getRegRef(DFG); 406 RegisterRef DR = DA.Addr->getRegRef(DFG); 477 RegisterRef [all...] |
H A D | RDFGraph.cpp | 57 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) { 111 << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>'; 310 OS << ' ' << Print<RegisterRef>(I, P.G); 324 << '<' << Print<RegisterRef>(I->Addr->getRegRef(P.G), P.G) << '>'; 408 RegisterRef RefNode::getRegRef(const DataFlowGraph &G) const { 418 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { 755 LR.insert(RegisterRef(R)); 758 LR.insert(RegisterRef(R)); 816 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { 832 RegisterRef R [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.h | 38 using EqualityMap = std::map<RegisterRef, RegisterRef>; 54 NodeId getLocalReachingDef(RegisterRef RefRR, NodeAddr<InstrNode*> IA);
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H A D | RDFCopy.cpp | 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); 47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); 88 NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR, 110 dbgs() << ' ' << Print<RegisterRef>(J.first, DFG) << '=' 111 << Print<RegisterRef>(J.second, DFG); 121 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { 145 RegisterRef DR = DA.Addr->getRegRef(DFG); 149 RegisterRef SR = FR->second; 174 dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG) 175 << " with " << Print<RegisterRef>(S [all...] |
H A D | HexagonExpandCondsets.cpp | 177 struct RegisterRef { struct in class:__anon4118::HexagonExpandCondsets 178 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), function in struct:__anon4118::HexagonExpandCondsets::RegisterRef 180 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} function in struct:__anon4118::HexagonExpandCondsets::RegisterRef 182 bool operator== (RegisterRef RR) const { 185 bool operator!= (RegisterRef RR) const { return !operator==(RR); } 186 bool operator< (RegisterRef RR) const { 201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec); 202 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec); 220 MachineInstr *getReachingDefForPred(RegisterRef RD, 228 void renameInRange(RegisterRef R [all...] |
H A D | BitTracker.h | 37 struct RegisterRef; 53 RegisterCell get(RegisterRef RR) const; 54 void put(RegisterRef RR, const RegisterCell &RC); 55 void subst(RegisterRef OldRR, RegisterRef NewRR); 140 struct BitTracker::RegisterRef { struct in class:llvm::BitTracker 141 RegisterRef(unsigned R = 0, unsigned S = 0) function in struct:llvm::BitTracker::RegisterRef 143 RegisterRef(const MachineOperand &MO) function in struct:llvm::BitTracker::RegisterRef 396 uint16_t getRegBitWidth(const RegisterRef &RR) const; 398 RegisterCell getCell(const RegisterRef [all...] |
H A D | HexagonBitTracker.h | 27 using RegisterRef = BitTracker::RegisterRef;
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H A D | HexagonBlockRanges.h | 33 struct RegisterRef { struct in struct:llvm::HexagonBlockRanges 36 bool operator<(RegisterRef R) const { 40 using RegisterSet = std::set<RegisterRef>; 142 using RegToRangeMap = std::map<RegisterRef, RangeList>; 146 static RegisterSet expandToSubRegs(RegisterRef R,
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H A D | HexagonBitSimplify.cpp | 211 static bool getSubregMask(const BitTracker::RegisterRef &RR, 218 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH, 227 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI); 228 static bool isTransparentCopy(const BitTracker::RegisterRef &RD, 229 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI); 405 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR, 433 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH, 896 const BitTracker::RegisterRef [all...] |
H A D | HexagonBlockRanges.cpp | 262 RegisterRef R, const MachineRegisterInfo &MRI, 292 std::map<RegisterRef,IndexType> LastDef, LastUse; 303 auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) -> void { 323 RegisterRef R = { Op.getReg(), Op.getSubReg() }; 339 RegisterRef R = { Op.getReg(), Op.getSubReg() }; 364 RegisterRef R = { PR, 0 }; 371 for (RegisterRef R : Defs) 375 for (RegisterRef S : Defs) { 384 for (RegisterRef S : Clobbers) { 435 auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (RegisterRef [all...] |
H A D | BitTracker.cpp | 329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { 348 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, 375 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC, 726 RegisterRef RD = MI.getOperand(0); 728 RegisterRef RS = MI.getOperand(1); 730 RegisterRef RT = MI.getOperand(3); 745 RegisterRef RD = MI.getOperand(0); 746 RegisterRef RS = MI.getOperand(1); 805 RegisterRef DefRR(MD); 826 RegisterRef R [all...] |
H A D | HexagonOptAddrMode.cpp | 167 RegisterRef OffsetRR; 170 RegisterRef RR = UA.Addr->getRegRef(*DFG); 216 RegisterRef UR = UN.Addr->getRegRef(*DFG); 249 RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG)); 269 if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) 287 RegisterRef LRExtRR; 292 RegisterRef RR = UA.Addr->getRegRef(*DFG);
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H A D | HexagonRDFOpt.cpp | 113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
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H A D | HexagonBitTracker.cpp | 94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); 163 std::vector<BT::RegisterRef> Vector; 170 Vector[i] = BT::RegisterRef(MO); 178 const BT::RegisterRef &operator[](unsigned n) const { 965 BT::RegisterRef PD(DefR, 0); 1020 RegisterRef PR = BI.getOperand(0); 1191 RegisterRef RD = MD; 1220 RegisterRef RD = MI.getOperand(0); 1221 RegisterRef RS = MI.getOperand(1);
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H A D | HexagonFrameLowering.cpp | 2456 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), 2525 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86LoadValueInjectionLoadHardening.cpp | 370 RegisterRef DefReg = DFG.getPRI().normalize(Def.Addr->getRegRef(DFG)); 376 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) {
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