Searched refs:Rd (Results 1 - 16 of 16) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.h30 // parity(Rd) == parity(Ra).
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
160 if (Rd == Ra)
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
167 << Register::isPhysicalRegister(Rd) << '\n');
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
186 const LiveInterval &ld = LIs.getInterval(Rd);
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
248 if (Rd != Ra) {
250 << " to " << printReg(Rd, TR
362 Register Rd = MI.getOperand(0).getReg(); local
372 Register Rd = MI.getOperand(0).getReg(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp848 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
853 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
856 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
939 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
967 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
988 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1001 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1013 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1018 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1543 unsigned Rd local
1600 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1631 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1687 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1706 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
[all...]
/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1170 uint32_t Rd; // the destination register
1174 Rd = 7;
1178 Rd = Bits32(opcode, 15, 12);
1188 if (Rd == GetFramePointerRegisterNumber())
1196 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1231 uint32_t Rd; // the destination register
1234 Rd = 7;
1237 Rd = 12;
1244 if (Rd == GetFramePointerRegisterNumber())
1252 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, s
1291 uint32_t Rd; // the destination register local
1379 uint32_t Rd; // the destination register local
1621 uint32_t Rd; // the destination register local
1683 uint32_t Rd; // the destination register local
3158 uint32_t Rd, Rn; local
3224 uint32_t Rd, Rn, Rm; local
3759 uint32_t Rd; // the destination register local
3848 uint32_t Rd; // the destination register local
5823 uint32_t Rd, Rn; local
5893 uint32_t Rd, Rn, Rm; local
5972 uint32_t Rd; local
6040 uint32_t Rd, Rn; local
6116 uint32_t Rd, Rn, Rm; local
6205 uint32_t Rd, Rn; local
6281 uint32_t Rd, Rn, Rm; local
8847 uint32_t Rd, Rn; local
8926 uint32_t Rd, Rn, Rm; local
9016 uint32_t Rd, Rn; local
9093 uint32_t Rd, Rn, Rm; local
9180 uint32_t Rd; // the destination register local
9253 uint32_t Rd; // the destination register local
9331 uint32_t Rd; // the destination register local
9391 uint32_t Rd; // the destination register local
9460 uint32_t Rd; // the destination register local
9529 uint32_t Rd; // the destination register local
9609 uint32_t Rd; // the destination register local
9703 uint32_t Rd; // the destination register local
14252 WriteCoreRegOptionalFlags( Context &context, const uint32_t result, const uint32_t Rd, bool setflags, const uint32_t carry, const uint32_t overflow) argument
[all...]
H A DEmulateInstructionARM.h200 const uint32_t Rd, bool setflags,
205 const uint32_t Rd) {
207 return WriteCoreRegOptionalFlags(context, result, Rd, false);
328 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
356 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
359 // A8.6.215 SUB (SP minus immediate) -- Rd == ip
204 WriteCoreReg(Context &context, const uint32_t result, const uint32_t Rd) argument
/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
H A Dxray_mips64.cpp48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2216 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2442 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
2451 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2453 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2466 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2474 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2477 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2493 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local
2502 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres
2705 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3032 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3302 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3349 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3397 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3432 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3485 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3584 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3627 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4793 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4922 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4989 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5054 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5184 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5254 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5317 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5398 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5622 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
6650 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp326 unsigned Rd = fieldFromInstruction(Insn, 7, 5); local
328 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
336 unsigned Rd = fieldFromInstruction(Insn, 7, 5); local
338 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp325 Register Rd; member in struct:__anon4108::HexagonConstExtenders::ExtDesc
396 OffsetRange getOffsetRange(Register Rd) const;
499 if (ED.Rd.Reg != 0)
500 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
1127 // Get the allowable deviation from the current value of Rd by checking
1128 // all uses of Rd.
1129 OffsetRange HCE::getOffsetRange(Register Rd) const {
1131 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) {
1135 if (Rd !
[all...]
H A DHexagonFrameLowering.cpp143 // Rd = PS_alloca Rs, A
145 // Rd - address of the allocated space
2540 // Rd = alloca Rs, #A
2542 // If Rs and Rd are different registers, use this sequence:
2543 // Rd = sub(r29, Rs)
2545 // Rd = and(Rd, #-A) ; if necessary
2547 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2549 // Rd
2556 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
[all...]
H A DHexagonInstrInfo.cpp1258 Register Rd = Op0.getReg(); local
1266 if (Rd != Rs)
1267 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1268 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1270 if (Rd != Rt)
1271 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
3361 // Rd = Rs
3368 // Rd = #u6
3398 // Rd=#U6 ; jump #r9:2
3399 // Rd
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); local
196 switch (Rd) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1692 MCOperand &Rd = Inst.getOperand(0); local
1709 TmpInst.addOperand(Rd);
1723 if (Value == 0) { // convert to $Rd = $Rs
1725 MCOperand &Rd = Inst.getOperand(0); local
1727 TmpInst.addOperand(Rd);
1735 MCOperand &Rd = Inst.getOperand(0); local
1737 TmpInst.addOperand(Rd);
1923 MCOperand &Rd = Inst.getOperand(0); local
1926 TmpInst.addOperand(Rd);
/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp589 // integer d = UInt(Rd);
630 const uint32_t Rd = Bits32(opcode, 4, 0); local
634 const uint32_t d = UInt(Rd);
/freebsd-13-stable/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2556 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2622 pxor $Rd, $Rd
2652 por $T0d, $Rd
2663 movdqu $Rd, 16*3($val)
2742 pxor $Rd, $Rd
2766 por $T0d, $Rd
2774 movdqu $Rd, 16*3($val)

Completed in 304 milliseconds