Searched refs:Rcp (Results 1 - 4 of 4) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2610 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); 2612 B.buildFMul(S32, Rcp, B.buildFConstant(S32, BitsToFloat(0x5f7ffffc))); 2641 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); 2646 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); 2647 auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1); 3021 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) 3025 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); 3026 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags);
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H A D | AMDGPUCodeGenPrepare.cpp | 1106 Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); local 1107 Value *RcpY = Builder.CreateCall(Rcp, {FloatY});
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H A D | AMDGPUISelLowering.cpp | 1800 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); local 1801 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
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H A D | SIISelLowering.cpp | 8291 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); local 8293 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); 8295 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
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