Searched refs:RS2 (Results 1 - 7 of 7) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h55 bool SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, SDValue &Shamt);
H A DRISCVISelDAGToDAG.cpp419 // (SRL (AND (AssertSext RS2, i32), VC3), VC1)))
466 // (SRL (AND (AssertSext RS2, i32), VC3), VC1)))
476 bool RISCVDAGToDAGISel::SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, argument
498 RS2 = And.getOperand(0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp924 unsigned RS2 = getRegState(Op2); local
948 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
951 .addReg(Op2.getReg(), RS2, HiSR);
955 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
959 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
968 .addReg(Op2.getReg(), RS2, HiSR)
979 .addReg(Op2.getReg(), RS2, LoSR);
990 .addReg(Op2.getReg(), RS2, LoSR)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp137 MCOperand &RS2, MCOperand &Imm, MCOperand &RD,
143 LEASLInst.addOperand(RS2);
136 emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/
H A DCompileOnDemandLayer.h544 auto RS2 =
547 for (auto &S : RS2)
714 auto RS2 =
717 for (auto &S : RS2)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
143 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp1289 for (const RegisterSet &RS2 : RegisterSets)
1290 if (RS != RS2 &&
1291 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1293 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);

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