Searched refs:RHS1 (Results 1 - 7 of 7) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | SparseBitVector.h | 238 // RHS1 & ~RHS2 into this element
239 void intersectWithComplement(const SparseBitVectorElement &RHS1,
246 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
686 // Result of RHS1 & ~RHS2 is stored into this bitmap.
687 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
690 if (this == &RHS1) {
695 intersectWithComplement(RHS1, RHS2Copy);
701 ElementListConstIter Iter1 = RHS1.Elements.begin();
704 // If RHS1 is empty, we are done
705 // If RHS2 is empty, we still have to copy RHS1
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | GuardWidening.cpp | 505 ConstantInt *RHS0, *RHS1;
509 match(Cond1, m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) {
516 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue());
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1409 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); local
1412 if (LHS0 == RHS1 && RHS0 == LHS1) {
1415 std::swap(RHS0, RHS1);
1432 if (LHS0 == RHS0 && LHS1 == RHS1) {
1446 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP()))
2956 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); local
2963 PredR == CmpInst::ICMP_SGT && match(RHS1, m_AllOnes())) ||
2965 PredR == CmpInst::ICMP_SLT && match(RHS1, m_Zero()))) {
2972 PredR == CmpInst::ICMP_SLT && match(RHS1, m_Zero())) ||
2974 PredR == CmpInst::ICMP_SGT && match(RHS1, m_AllOne
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1864 Value *RHS0 = RHS->getOperand(0), *RHS1 = RHS->getOperand(1); local
1879 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) ||
1880 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1)))
1891 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) ||
1892 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1)))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 577 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, local
591 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5023 SDValue RHS1 = Op.getOperand(1); local
5040 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
5041 ? &RHS1
5047 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
5067 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
5073 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
5441 SDValue RHS1, RHS2; local
5443 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5449 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
11142 Register RHS1 local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5943 SDValue RHS1, RHS2;
5944 std::tie(RHS1, RHS2) = splitVector(Op.getOperand(1), DAG, dl);
5949 DAG.getNode(Op.getOpcode(), dl, LoVT, LHS1, RHS1),
22106 SDValue RHS1, RHS2;
22107 std::tie(RHS1, RHS2) = splitVector(Op.getOperand(1), DAG, dl);
22113 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC),
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