| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorPrint.cpp | 54 const HexagonInstrInfo *QII = nullptr; member in class:__anon4154::HexagonVectorPrint
98 const DebugLoc &DL, const HexagonInstrInfo *QII,
103 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
135 QII = QST->getInstrInfo();
185 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
189 MII, DL, QII, Fn);
191 MII, DL, QII, Fn);
194 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
96 addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const HexagonInstrInfo *QII, MachineFunction &Fn) argument
|
| H A D | HexagonPeephole.cpp | 82 const HexagonInstrInfo *QII; member in struct:__anon4144::HexagonPeephole
113 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
238 if (QII->isPredicated(MI)) {
251 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
252 MI.setDesc(QII->get(NewOp));
281 QII->get(NewOp), MI.getOperand(0).getReg())
|
| H A D | HexagonNewValueJump.cpp | 96 const HexagonInstrInfo *QII; member in struct:__anon4141::HexagonNewValueJump
117 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, argument
124 if (QII->isPredicated(*II))
143 if (QII->isSolo(*II))
146 if (QII->isFloat(*II))
238 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, argument
460 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
575 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
616 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
626 if (!canBeFeederToNewValueJump(QII, QR
[all...] |
| H A D | HexagonSubtarget.cpp | 146 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII); local
149 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
155 if (!QII->isHVXVec(MI2))
326 const HexagonInstrInfo *QII = getInstrInfo(); local
331 if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
332 isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
366 if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
367 isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
411 auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
414 if (QII
[all...] |
| H A D | HexagonMachineScheduler.cpp | 69 const HexagonInstrInfo &QII) {
74 if (QII.mayBeCurLoad(*SUd->getInstr()))
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
121 const auto &QII = *QST.getInstrInfo(); local
127 if (hasDependence(Packet[i], SU, QII))
131 if (hasDependence(SU, Packet[i], QII))
690 auto &QII = *QST.getInstrInfo(); local
691 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
68 hasDependence(const SUnit *SUd, const SUnit *SUu, const HexagonInstrInfo &QII) argument
|
| H A D | HexagonVLIWPacketizer.cpp | 950 const HexagonInstrInfo *QII) {
953 assert(QII->isPredicated(MI) && "Must be predicated instruction");
949 getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII) argument
|