Searched refs:PartTy (Results 1 - 6 of 6) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCallLowering.cpp | 242 Type *PartTy = EVT(RegVT).getTypeForEVT(Ctx); local 243 LLT PartLLT = getLLTForType(*PartTy, DL); 251 SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags); local 276 LLT PartTy) { 280 const unsigned PartSize = PartTy.getSizeInBits(); 282 if (SrcTy.isVector() && !PartTy.isVector() && 299 LLT BigTy = getMultipleType(PartTy, NumRoundedParts); 271 unpackRegsToOrigType(MachineIRBuilder &B, ArrayRef<Register> DstRegs, Register SrcReg, const CallLowering::ArgInfo &Info, LLT SrcTy, LLT PartTy) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 82 Type *PartTy = PartVT.getTypeForEVT(Context); local 86 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), 87 PartTy, OrigArg.Flags};
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.h | 186 /// \p PartRegs must be registers of type \p PartTy. 188 /// If \p ResultTy does not evenly break into \p PartTy sized pieces, the 191 LLT PartTy, ArrayRef<Register> PartRegs,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | SROA.cpp | 3974 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8); 3976 auto *PartPtrTy = PartTy->getPointerTo(AS); 3978 PartTy, 4109 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8); 4110 auto *LoadPartPtrTy = PartTy->getPointerTo(LI->getPointerAddressSpace()); 4111 auto *StorePartPtrTy = PartTy->getPointerTo(SI->getPointerAddressSpace()); 4121 PartTy,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 196 LLT ResultTy, LLT PartTy, 208 if (PartTy.isVector()) 215 unsigned PartSize = PartTy.getSizeInBits(); 3221 // Split the load/store into PartTy sized pieces starting at Offset. If this 3223 // of ValRegs should be PartTy. Returns the next offset that needs to be 3225 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3228 unsigned PartSize = PartTy.getSizeInBits(); 3241 Register Dst = MRI.createGenericVirtualRegister(PartTy); 195 insertParts(Register DstReg, LLT ResultTy, LLT PartTy, ArrayRef<Register> PartRegs, LLT LeftoverTy, ArrayRef<Register> LeftoverRegs) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2878 // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)". 2879 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) local 2882 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
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