Searched refs:PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-13-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h5377 #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2 (0xffffff<<0) // Insert Lane Skew for Transmit (not supported for x16). Optional feature that causes the core to insert skew between Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol time. For example, the value 010b for a Lane forces a skew of two symbol times for that Lane. The maximum skew value for any Lane is 5 symbol times. Note: This register field is sticky. macro
[all...]

Completed in 1241 milliseconds