/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 568 int64_t Offset1 = Const->getSExtValue(); local 569 int64_t CombinedOffset = Offset1 + Offset2; 583 int64_t Offset1 = GA->getOffset(); local 584 int64_t CombinedOffset = Offset1 + Offset2; 593 int64_t Offset1 = CP->getOffset(); local 594 int64_t CombinedOffset = Offset1 + Offset2;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 244 int64_t Offset1, Offset2; local 245 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 246 Offset1 == Offset2 || 252 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 253 Offsets.push_back(Offset1); 256 if (Offset2 < Offset1)
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H A D | DAGCombiner.cpp | 14471 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); local 14482 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; 14483 else CNV = CNV - Offset1; 16572 int64_t Offset1 = LoadNodes[1].OffsetFromBase; local 16574 if (Offset0 - Offset1 == ElementSizeBytes &&
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 289 int64_t Offset1; local 291 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); 297 if (((Offset0 ^ Offset1) & 0x18) != 0)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 409 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 420 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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H A D | X86InstrInfo.cpp | 6433 int64_t &Offset1, int64_t &Offset2) const { 6625 Offset1 = Disp1->getSExtValue(); 6631 int64_t Offset1, int64_t Offset2, 6633 assert(Offset2 > Offset1); 6634 if ((Offset2 - Offset1) / 8 > 64) 6432 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 6630 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MicroMipsSizeReduction.cpp | 400 int64_t Offset1, Offset2; local 401 if (!GetImm(MI1, 2, Offset1)) 409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
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/freebsd-13-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
H A D | ContainerModeling.cpp | 139 SymbolRef Offset1, 973 SymbolRef Offset1, 978 return compare(State, Pos.getOffset(), Offset1, Opc1) &&
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetInstrInfo.h | 1224 int64_t &Offset1, 1238 int64_t Offset1, int64_t Offset2, 1223 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 1237 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | SeparateConstOffsetFromGEP.cpp | 1328 Value *Offset1 = First->getOperand(1); local 1331 Second->setOperand(1, Offset1);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 258 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 270 int64_t Offset1, int64_t Offset2,
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H A D | ARMBaseInstrInfo.cpp | 1892 int64_t &Offset1, 1953 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1973 int64_t Offset1, int64_t Offset2, 1978 assert(Offset2 > Offset1); 1980 if ((Offset2 - Offset1) / 8 > 64) 1891 areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const argument 1972 shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.h | 184 int64_t &Offset1, 198 int64_t Offset1, unsigned NumLoads) const override;
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H A D | AMDGPUISelDAGToDAG.cpp | 207 SDValue &Offset1) const; 1236 SDValue &Offset1) const { 1249 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); 1284 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); 1301 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); 1310 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
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H A D | SIInstrInfo.cpp | 158 int64_t &Offset1) const { 194 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue(); 219 Offset1 = Load1Offset->getZExtValue(); 252 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); 310 unsigned Offset1 = Offset1Op->getImm(); local 311 if (Offset0 + 1 != Offset1) 511 int64_t Offset0, int64_t Offset1, 513 assert(Offset1 > Offset0 && 519 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); 2784 int64_t Offset0, Offset1; 510 shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const argument [all...] |
H A D | SILoadStoreOptimizer.cpp | 1780 uint64_t Offset1 = Src1->getImm(); 1787 Addr.Offset = (*Offset0P & 0x00000000ffffffff) | (Offset1 << 32);
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H A D | AMDGPUInstructionSelector.cpp | 1147 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) | local 1151 Offset1 |= (CountDw - 1) << 6; 1153 unsigned Offset = Offset0 | (Offset1 << 8);
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H A D | SIISelLowering.cpp | 6661 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) | local 6665 Offset1 |= (CountDw - 1) << 6; 6667 unsigned Offset = Offset0 | (Offset1 << 8);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 2499 int64_t Offset1, unsigned Opcode1, int FI2, 2516 ObjectOffset1 += Offset1; 2566 int64_t Offset1 = FirstLdSt.getOperand(2).getImm(); 2567 if (isUnscaledLdSt(FirstOpc) && !scaleOffset(FirstOpc, Offset1)) 2575 if (Offset1 > 63 || Offset1 < -64) 2581 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && 2586 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, 2590 assert(Offset1 <= Offset2 && "Caller should have ordered offsets."); 2592 return Offset1 2498 shouldClusterFI(const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachinePipeliner.cpp | 764 int64_t Offset1, Offset2; local 766 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, 772 (int)Offset1 < (int)Offset2) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | ValueTracking.cpp | 6539 auto Offset1 = getOffsetFromIndex(GEP1, Idx, DL); local 6541 if (!Offset1 || !Offset2) 6543 return *Offset2 - *Offset1;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 12966 int64_t Offset1 = 0, Offset2 = 0; local 12967 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG); 12969 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes)) 12975 Offset1 = 0; 12977 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); 12980 return Offset1 == (Offset2 + Dist*Bytes);
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