Searched refs:NumVecs (Results 1 - 6 of 6) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp195 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
198 /// For NumVecs <= 2, QOpcodes1 is not used.
199 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
203 /// SelectVST - Select NEON store intrinsics. NumVecs should
206 /// For NumVecs <= 2, QOpcodes1 is not used.
207 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
211 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
215 unsigned NumVecs, const uint16_t *DOpcodes,
267 /// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
270 /// pointer points to a set of NumVecs su
1914 GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs, bool is64BitVector) argument
2050 isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) argument
2055 SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
2197 SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
2351 SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) argument
2730 SelectMVE_VLD(SDNode *N, unsigned NumVecs, const uint16_t *const *Opcodes, bool HasWriteback) argument
2890 SelectVLDDup(SDNode *N, bool IsIntrinsic, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument
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H A DARMISelLowering.cpp13840 unsigned NumVecs = 0; local
13846 NumVecs = 1; break;
13848 NumVecs = 2; break;
13850 NumVecs = 3; break;
13852 NumVecs = 4; break;
13860 NumVecs = 2; isLaneOp = true; break;
13862 NumVecs = 3; isLaneOp = true; break;
13864 NumVecs = 4; isLaneOp = true; break;
13866 NumVecs = 1; isLoadOp = false; break;
13868 NumVecs
14073 unsigned NumVecs = 0; local
14166 unsigned NumVecs = 0; local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp235 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
242 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
244 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
246 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
247 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
248 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
262 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
263 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
264 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
265 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigne
1238 SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt) argument
1355 SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1381 SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1437 SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale, unsigned Opc_ri, unsigned Opc_rr) argument
1470 SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1490 SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale, unsigned Opc_rr, unsigned Opc_ri) argument
1532 SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1588 SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1627 SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1682 SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1711 SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
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H A DAArch64ISelLowering.cpp9339 template <unsigned NumVecs>
9348 for (unsigned I = 0; I < NumVecs; ++I)
9352 // memVT is `NumVecs * VT`.
9354 EC * NumVecs);
12771 unsigned NumVecs = 0; local
12776 NumVecs = 2; break;
12778 NumVecs = 3; break;
12780 NumVecs = 4; break;
12782 NumVecs = 2; IsStore = true; break;
12784 NumVecs
14108 uint64_t NumVecs = TupleLanes / NumLanes; local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp778 unsigned NumVecs) {
781 for (unsigned j = 0; j < NumVecs; j++)
837 unsigned NumVecs = Vecs.size(); local
838 assert(NumVecs > 1 && "Should be at least two vectors");
844 for (unsigned i = 0; i < NumVecs - 1; i += 2) {
846 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
853 if (NumVecs % 2 != 0)
854 TmpList.push_back(ResList[NumVecs - 1]);
857 NumVecs = ResList.size();
858 } while (NumVecs >
777 createInterleaveMask(unsigned VF, unsigned NumVecs) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h493 /// This function creates a shuffle mask for interleaving \p NumVecs vectors of
497 /// <0, VF, VF * 2, ..., VF * (NumVecs - 1), 1, VF + 1, VF * 2 + 1, ...>
499 /// For example, the mask for VF = 4 and NumVecs = 2 is:
502 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);

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