Searched refs:NewOpc (Results 1 - 25 of 56) sorted by relevance

123

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp517 unsigned NewOpc; local
520 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
521 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
522 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
523 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
525 OutMI.setOpcode(NewOpc);
549 unsigned NewOpc; local
552 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
553 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
554 case X86::VMOVAPDYrr: NewOpc
574 unsigned NewOpc; local
617 unsigned NewOpc; local
689 unsigned NewOpc; local
853 unsigned NewOpc; local
878 unsigned NewOpc; local
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H A DX86EvexToVex.cpp147 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { argument
148 (void)NewOpc;
155 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
171 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
172 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
257 unsigned NewOpc = I->VexOpcode; local
262 if (!performCustomAdjustments(MI, NewOpc))
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H A DX86FixupLEAs.cpp592 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local
598 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
604 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
630 unsigned NewOpc = local
632 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
636 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); local
637 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
663 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); local
664 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
685 unsigned NewOpc local
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H A DX86ISelDAGToDAG.cpp928 unsigned NewOpc; local
931 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break;
932 case ISD::STRICT_FP_ROUND: NewOpc = X86ISD::STRICT_VFPROUND; break;
933 case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break;
934 case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break;
935 case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break;
936 case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break;
941 CurDAG->getNode(NewOpc, SDLoc(N), {N->getValueType(0), MVT::Other},
945 CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0),
961 unsigned NewOpc; local
983 unsigned NewOpc; local
1369 unsigned NewOpc; local
1412 unsigned NewOpc; local
3105 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, local
3120 unsigned NewOpc = local
3210 unsigned NewOpc = SelectRegOpcode(Opc); local
3616 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; local
3632 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; local
3656 unsigned NewOpc = NVT == MVT::i64 ? X86::SHR64ri : X86::SHR32ri; local
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H A DX86InstructionSelector.cpp530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); local
531 if (NewOpc == Opc)
537 I.setDesc(TII.get(NewOpc));
572 unsigned NewOpc = getLeaOP(Ty, STI); local
573 I.setDesc(TII.get(NewOpc));
623 unsigned NewOpc = getLeaOP(Ty, STI); local
625 I.setDesc(TII.get(NewOpc));
655 unsigned NewOpc; local
658 NewOpc = X86::MOV8ri;
661 NewOpc
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp224 unsigned OpNum, NewOpc; local
227 NewOpc = Hexagon::L2_loadri_io;
231 NewOpc = Hexagon::L2_loadrd_io;
235 NewOpc = Hexagon::V6_vL32b_ai;
239 NewOpc = Hexagon::S2_storeri_io;
243 NewOpc = Hexagon::S2_storerd_io;
247 NewOpc = Hexagon::V6_vS32b_ai;
273 MI.setDesc(HII.get(NewOpc));
H A DHexagonGenPredicate.cpp388 unsigned NewOpc = getPredForm(Opc); local
390 if (NewOpc == 0) {
393 NewOpc = Hexagon::C2_not;
396 NewOpc = TargetOpcode::COPY;
423 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
H A DHexagonCopyToCombine.cpp872 unsigned NewOpc; local
874 NewOpc = Hexagon::A2_combinew;
877 NewOpc = Hexagon::V6_vcombine;
881 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp595 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, argument
617 switch (NewOpc) {
619 NewOpc = Mips::BEQZC;
622 NewOpc = Mips::BNEZC;
625 NewOpc = Mips::BGEZC;
628 NewOpc = Mips::BLTZC;
631 NewOpc = Mips::BEQZC64;
634 NewOpc = Mips::BNEZC64;
639 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
645 if (NewOpc
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H A DMipsSEInstrInfo.h98 unsigned NewOpc) const;
H A DMipsInstrInfo.h152 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
H A DMipsSEISelLowering.h78 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1325 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local
1326 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1457 unsigned NewOpc; local
1459 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1461 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1465 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1467 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1482 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1492 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc
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H A DThumb2InstrInfo.cpp531 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
533 MI.setDesc(TII.get(NewOpc));
564 unsigned NewOpc = Opcode;
574 NewOpc = immediateOffsetOpcode(Opcode);
586 NewOpc = negativeOffsetOpcode(Opcode);
591 NewOpc = positiveOffsetOpcode(Opcode);
651 if (NewOpc != Opcode)
652 MI.setDesc(TII.get(NewOpc));
696 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
H A DARMConstantIslandPass.cpp1732 unsigned NewOpc = 0; local
1739 NewOpc = ARM::tLEApcrel;
1746 NewOpc = ARM::tLDRpci;
1753 if (!NewOpc)
1766 U.MI->setDesc(TII->get(NewOpc));
1783 unsigned NewOpc = 0;
1789 NewOpc = ARM::tB;
1794 NewOpc = ARM::tBcc;
1799 if (NewOpc) {
1804 Br.MI->setDesc(TII->get(NewOpc));
1817 unsigned NewOpc = 0; member in struct:ImmCompare
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H A DARMInstructionSelector.cpp901 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); local
902 if (NewOpc == I.getOpcode())
904 I.setDesc(TII.get(NewOpc));
1097 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); local
1098 if (NewOpc == G_LOAD || NewOpc == G_STORE)
1101 if (ValSize == 1 && NewOpc == Opcodes.STORE8) {
1119 I.setDesc(TII.get(NewOpc));
1121 if (NewOpc == ARM::LDRH || NewOpc
[all...]
H A DThumbRegisterInfo.cpp404 unsigned NewOpc = convertToNonSPOpcode(Opcode);
405 if (NewOpc != Opcode && FrameReg != ARM::SP)
406 MI.setDesc(TII.get(NewOpc));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); local
255 assert(NewOpc != 0 && "Unknown merged node opcode");
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); local
293 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
H A DAArch64CondBrTuning.cpp100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); local
106 TII->get(NewOpc), NewDestReg);
H A DAArch64FrameLowering.cpp832 unsigned NewOpc; local
838 NewOpc = AArch64::STPXpre;
842 NewOpc = AArch64::STPDpre;
846 NewOpc = AArch64::STPQpre;
850 NewOpc = AArch64::STRXpre;
853 NewOpc = AArch64::STRDpre;
856 NewOpc = AArch64::STRQpre;
859 NewOpc = AArch64::LDPXpost;
863 NewOpc = AArch64::LDPDpost;
867 NewOpc
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp213 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; local
223 assert(MI.getOpcode() != NewOpc);
224 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp668 unsigned NewOpc = Node->getOpcode(); local
671 if (NewOpc == ISD::FP_TO_UINT &&
673 NewOpc = ISD::FP_TO_SINT;
675 if (NewOpc == ISD::STRICT_FP_TO_UINT &&
677 NewOpc = ISD::STRICT_FP_TO_SINT;
682 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
686 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0));
693 NewOpc = ISD::AssertZext;
695 NewOpc = ISD::AssertSext;
697 Promoted = DAG.getNode(NewOpc, d
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp3141 unsigned NewOpc; local
3144 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
3145 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
3146 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
3147 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
3148 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
3149 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
3150 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
3151 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
3152 case X86::VMOVDQUYrr: NewOpc
3170 unsigned NewOpc; local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGISel.h326 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);

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