Searched refs:MulRHS (Results 1 - 2 of 2) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1253 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1); local
1257 std::swap(MulLHS, MulRHS);
1259 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1260 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1639 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1); local
1643 std::swap(MulLHS, MulRHS);
1645 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1646 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10040 SDValue MulRHS = LHS.getOperand(1); local
10045 numBitsUnsigned(MulRHS, DAG) <= 32) {
10047 MulRHS = DAG.getZExtOrTrunc(MulRHS, SL, MVT::i32);
10049 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, false);
10052 if (numBitsSigned(MulLHS, DAG) < 32 && numBitsSigned(MulRHS, DAG) < 32) {
10054 MulRHS = DAG.getSExtOrTrunc(MulRHS, SL, MVT::i32);
10056 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, true);
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