Searched refs:LogicOp (Results 1 - 5 of 5) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp899 struct LogicOp { struct in namespace:__anon4334
900 LogicOp() = default;
901 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) function in struct:__anon4334::LogicOp
913 static LogicOp interpretAndImmediate(unsigned Opcode) {
915 case SystemZ::NILMux: return LogicOp(32, 0, 16);
916 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
917 case SystemZ::NILL64: return LogicOp(64, 0, 16);
918 case SystemZ::NILH64: return LogicOp(64, 16, 16);
919 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
920 case SystemZ::NIHH64: return LogicOp(6
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2509 SDValue computeLogicOpInGPR(SDValue LogicOp);
2683 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { argument
2684 assert(isLogicOp(LogicOp.getOpcode()) &&
2686 assert(LogicOp.getValueType() == MVT::i1 &&
2688 SDLoc dl(LogicOp);
2692 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2713 LHS = getLogicOperand(LogicOp.getOperand(0));
2714 RHS = getLogicOperand(LogicOp.getOperand(1));
2731 switch (LogicOp.getOpcode()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7760 BinaryOperator *LogicOp; local
7762 if (!match(BB.getTerminator(), m_Br(m_OneUse(m_BinOp(LogicOp)), TBB, FBB)))
7775 if (match(LogicOp, m_And(m_OneUse(m_Value(Cond1)),
7778 else if (match(LogicOp, m_Or(m_OneUse(m_Value(Cond1)),
7798 LogicOp->eraseFromParent();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7505 SDValue LogicOp = Shift->getOperand(0); local
7506 if (!LogicOp.hasOneUse())
7509 unsigned LogicOpcode = LogicOp.getOpcode();
7548 if (matchFirstShift(LogicOp.getOperand(0), X, C0Val))
7549 Y = LogicOp.getOperand(1);
7550 else if (matchFirstShift(LogicOp.getOperand(1), X, C0Val))
7551 Y = LogicOp.getOperand(0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp21255 unsigned LogicOp = IsFABS ? X86ISD::FAND :
21261 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
21266 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
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