| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 271 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, argument
275 LoReg = getSubReg(Reg, AVR::sub_lo);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 765 Register LoReg = LoOperand.getReg(); local
776 .addReg(LoReg, LoRegKillFlag);
784 .addReg(LoReg, LoRegKillFlag);
791 .addReg(LoReg, LoRegKillFlag);
799 .addReg(LoReg, LoRegKillFlag);
803 // DoubleRegDest = combine #HiImm, LoReg
806 .addReg(LoReg, LoRegKillFlag);
864 Register LoReg = LoOperand.getReg(); local
871 // DoubleRegDest = combine HiReg, LoReg
883 .addReg(LoReg, LoRegKillFla
[all...] |
| H A D | HexagonFrameLowering.cpp | 1126 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); local
1128 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1740 Register LoReg = MRI->createVirtualRegister(DstRC); local
1742 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg)
1758 .addReg(LoReg, RegState::Implicit);
1781 .addReg(LoReg)
1990 Register LoReg = MRI->createVirtualRegister(RC); local
1993 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
2000 .addReg(LoReg)
2045 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
2050 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg)
2063 .addReg(LoReg)
2082 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
2361 Register LoReg = MRI->createVirtualRegister(&RegRC); local
[all...] |
| H A D | SILoadStoreOptimizer.cpp | 190 Register LoReg; member in struct:__anon3979::SILoadStoreOptimizer::BaseRegisters
1650 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 ||
1672 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg)
1783 Addr.Base.LoReg = BaseLo.getReg();
1831 << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";);
1887 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg ||
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4663 unsigned LoReg, ROpc, MOpc; local
4667 LoReg = X86::AL;
4672 LoReg = X86::AX;
4677 LoReg = X86::EAX;
4682 LoReg = X86::RAX;
4697 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
4742 unsigned LoReg, HiReg; local
4755 LoReg = UseMULX ? X86::EDX : X86::EAX;
4765 LoReg = UseMULX ? X86::RDX : X86::RAX;
4779 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
4881 unsigned LoReg, HiReg, ClrReg; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); local
325 std::swap(LoReg, HiReg);
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
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| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); local
857 .addReg(LoReg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1786 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
1787 if (JumpReg == LoReg)
1789 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
1806 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; local
1807 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
1812 .addReg(LoReg, RegState::Kill);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1219 Register LoReg = MI.getOperand(0).getReg(); local
1227 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg)
1255 Register LoReg = MI.getOperand(0).getReg(); local
1266 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
1288 Register LoReg = MI.getOperand(1).getReg(); local
1297 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12247 Register LoReg = MI.getOperand(0).getReg(); local
12251 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
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