Searched refs:LiveIn (Results 1 - 25 of 26) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp54 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
55 if (LiveIn.first == VReg)
56 return LiveIn.second.isSExt();
61 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
62 if (LiveIn.first == VReg)
63 return LiveIn.second.isZExt();
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h122 /// LiveIn - Work list of blocks where the live-in value has yet to be
126 SmallVector<LiveInBlock, 16> LiveIn; member in class:llvm::LiveRangeCalc
142 /// live in are added to the LiveIn array, and the function returns false.
154 /// blocks in LiveIn. Create PHI-def values as required to preserve SSA form.
160 /// Transfer information from the LiveIn vector to the live ranges and update
246 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DRDFLiveness.h137 void traverse(MachineBasicBlock *B, RefMap &LiveIn);
H A DMIRYamlMapping.h207 static void mapping(IO &YamlIO, MachineFunctionLiveIn &LiveIn) { argument
208 YamlIO.mapRequired("reg", LiveIn.Register);
210 "virtual-reg", LiveIn.VirtualRegister,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeCalc.cpp61 LiveIn.clear();
66 for (const LiveInBlock &I : LiveIn) {
86 LiveIn.clear();
271 LiveIn.clear();
312 // Multiple values were found, so transfer the work list to the LiveIn array
314 LiveIn.reserve(WorkList.size());
322 LiveIn.back().Kill = Use;
340 for (LiveInBlock &I : LiveIn) {
H A DRDFLiveness.cpp802 RefMap LiveIn; local
803 traverse(&MF.front(), LiveIn);
874 BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
875 CopyLiveIns(B, LiveIn);
928 void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { argument
929 // The LiveIn map, for each (physical) register, contains the set of live
960 LiveIn[S.first].insert(S.second.begin(), S.second.end());
969 dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
976 LiveIn[
[all...]
H A DStackColoring.cpp396 BitVector LiveIn; member in struct:__anon3590::StackColoring::BlockLifetimeInfo
547 dumpBV("LIVE_IN", BlockInfo.LiveIn);
774 // Compute LiveIn by unioning together the LiveOut sets of all preds.
797 // Update block LiveIn set, noting whether it has changed.
798 if (LocalLiveIn.test(BlockInfo.LiveIn)) {
800 BlockInfo.LiveIn |= LocalLiveIn;
828 for (int pos = MBBLiveness.LiveIn.find_first(); pos != -1;
829 pos = MBBLiveness.LiveIn.find_next(pos)) {
H A DBranchRelaxation.cpp455 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins())
456 BranchBB->addLiveIn(LiveIn);
H A DMIRPrinter.cpp311 yaml::MachineFunctionLiveIn LiveIn; local
312 printRegMIR(LI.first, LiveIn.Register, TRI);
314 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
315 MF.LiveIns.push_back(LiveIn);
H A DSplitKit.h126 bool LiveIn; ///< Current reg is live in. member in struct:llvm::SplitAnalysis::BlockInfo
H A DRegAllocGreedy.cpp1192 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
1206 if (BI.LiveIn) {
1417 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1594 if (EnableAdvancedRASplitCost && Cand.Intf.hasInterference() && BI.LiveIn &&
1615 if (BI.LiveIn)
1692 if (BI.LiveIn) {
2142 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
2323 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
2417 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
H A DMachineCSE.cpp690 auto LiveIn = PhysDefs.pop_back_val(); local
691 if (!MBB->isLiveIn(LiveIn.second))
692 MBB->addLiveIn(LiveIn.second);
H A DRegisterPressure.cpp916 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
917 if (LiveIn.any()) {
918 discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
919 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
920 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
1335 /// This assumes that the current LiveIn set is sufficient.
H A DSplitKit.cpp261 BI.LiveIn = LVI->start <= Start;
264 if (!BI.LiveIn) {
291 BI.LiveIn = false;
1573 if (BI.LiveIn && BI.LiveOut)
1723 assert(BI.LiveIn && "Must be live-in");
1813 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1821 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
H A DMachineBasicBlock.cpp538 bool LiveIn = isLiveIn(PhysReg);
544 if (LiveIn)
557 if (!LiveIn)
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DStackLifetime.h43 : Begin(Size), End(Size), LiveIn(Size), LiveOut(Size) {}
52 BitVector LiveIn; member in struct:llvm::StackLifetime::BlockLifetimeInfo
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DStackLifetime.cpp173 // Compute LiveIn by unioning together the LiveOut sets of all preds.
204 // Update block LiveIn set, noting whether it has changed.
205 if (LocalLiveIn.test(BlockInfo.LiveIn)) {
206 BlockInfo.LiveIn |= LocalLiveIn;
231 // LiveIn ranges start at the first instruction.
233 if (BlockInfo.LiveIn.test(AllocaNo)) {
282 << ", livein " << BlockInfo.LiveIn << ", liveout "
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp566 for (const auto &LiveIn : YamlMF.LiveIns) {
568 if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error))
569 return error(Error, LiveIn.Register.SourceRange);
571 if (!LiveIn.VirtualRegister.Value.empty()) {
573 if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value,
575 return error(Error, LiveIn.VirtualRegister.SourceRange);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInsertSkips.cpp239 for (auto LiveIn : MBB.liveins())
240 SplitBB->addLiveIn(LiveIn);
H A DAMDGPULegalizerInfo.h93 Register LiveIn, Register PhyReg) const;
H A DAMDGPULegalizerInfo.cpp2401 Register LiveIn,
2408 if (!MRI.getVRegDef(LiveIn)) {
2416 B.buildCopy(LiveIn, PhyReg);
2421 return LiveIn;
2431 Register LiveIn = MRI.getLiveInVirtReg(PhyReg);
2432 if (!LiveIn) {
2433 LiveIn = MRI.createGenericVirtualRegister(Ty);
2434 MRI.addLiveIn(PhyReg, LiveIn);
2441 return LiveIn;
2443 return insertLiveInCopy(B, MRI, LiveIn, PhyRe
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H A DGCNSchedStrategy.cpp461 auto LiveIn = std::move(LiveInIt->second); local
462 RPTracker.reset(*MBB->begin(), &LiveIn);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp243 MapVector<BasicBlock *, SetVector<Value *>> LiveIn; member in struct:__anon4702::GCPtrLivenessData
2702 // KILL/Def - Remove this definition from LiveIn
2710 // USE - Add to the LiveIn set for this instruction
2780 checkBasicSSA(DT, Data.LiveIn[&BB], BB.getTerminator());
2801 Data.LiveIn[&BB] = Data.LiveSet[&BB];
2802 Data.LiveIn[&BB].set_union(Data.LiveOut[&BB]);
2803 Data.LiveIn[&BB].set_subtract(Data.KillSet[&BB]);
2804 if (!Data.LiveIn[&BB].empty())
2817 assert(Data.LiveIn.count(Succ));
2818 LiveOut.set_union(Data.LiveIn[Suc
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/tools/llvm-objdump/
H A Dllvm-objdump.cpp618 bool LiveIn = false;
750 ActiveCols[ColIdx].LiveIn = LV.liveAtAddress(ThisAddr);
754 << ColIdx << ": LiveIn=" << ActiveCols[ColIdx].LiveIn
757 if (!ActiveCols[ColIdx].LiveIn && !ActiveCols[ColIdx].LiveOut)
769 bool LiveIn = LV.liveAtAddress(ThisAddr);
771 if (!LiveIn && !LiveOut)
777 << ColIdx << ": LiveIn=" << LiveIn
780 ActiveCols[ColIdx].LiveIn
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1007 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1056 getLiveInRegsAt(LiveIn, MI);
1057 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));

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