Searched refs:LHS1 (Results 1 - 5 of 5) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1408 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); local
1412 if (LHS0 == RHS1 && RHS0 == LHS1) {
1432 if (LHS0 == RHS0 && LHS1 == RHS1) {
1436 return getFCmpValue(NewPred, LHS0, LHS1, Builder);
1446 if (match(LHS1, m_PosZeroFP()) && match(RHS1, m_PosZeroFP()))
2955 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); local
2962 if ((PredL == CmpInst::ICMP_SGT && match(LHS1, m_AllOnes()) &&
2964 (PredL == CmpInst::ICMP_SLT && match(LHS1, m_Zero()) &&
2971 if ((PredL == CmpInst::ICMP_SGT && match(LHS1, m_AllOnes()) &&
2973 (PredL == CmpInst::ICMP_SLT && match(LHS1, m_Zer
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1863 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); local
1879 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) ||
1880 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1)))
1891 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) ||
1892 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1)))
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 563 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, local
591 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5022 SDValue LHS1 = Op.getOperand(0); local
5040 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
5047 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
5067 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
5073 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
5440 SDValue LHS1, LHS2; local
5442 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5449 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS
11131 Register LHS1 = MI.getOperand(1).getReg(); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5939 SDValue LHS1, LHS2;
5940 std::tie(LHS1, LHS2) = splitVector(Op.getOperand(0), DAG, dl);
5949 DAG.getNode(Op.getOpcode(), dl, LoVT, LHS1, RHS1),
22102 SDValue LHS1, LHS2;
22103 std::tie(LHS1, LHS2) = splitVector(Op.getOperand(0), DAG, dl);
22113 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC),
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