Searched refs:LE_CSR0 (Results 1 - 5 of 5) sorted by relevance

/freebsd-13-stable/sys/dev/le/
H A Dam7990.c405 isr = (*sc->sc_rdcsr)(sc, LE_CSR0);
423 (*sc->sc_wrcsr)(sc, LE_CSR0, isr & ~(LE_C0_INEA | LE_C0_TDMD |
481 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
557 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD);
587 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
610 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
H A Dam79900.c443 isr = (*sc->sc_rdcsr)(sc, LE_CSR0);
461 (*sc->sc_wrcsr)(sc, LE_CSR0, isr & ~(LE_C0_INEA | LE_C0_TDMD |
519 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA);
596 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD);
626 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
648 if_printf(ifp, "status %04x\n", (*sc->sc_rdcsr)(sc, LE_CSR0));
H A Dlance.c263 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP);
289 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP);
319 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INIT);
323 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON)
326 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON) {
328 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT);
H A Dif_le_isa.c218 le_isa_wrcsr(sc, LE_CSR0, LE_C0_STOP);
220 if (le_isa_rdcsr(sc, LE_CSR0) != LE_C0_STOP) {
H A Dlancereg.h142 #define LE_CSR0 0x0000 /* Control and status register */ macro

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