Searched refs:Immr (Results 1 - 3 of 3) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1838 SDValue &Opd0, unsigned &Immr,
1865 Immr = ShiftImm;
1917 unsigned &Immr, unsigned &Imms,
1931 if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
1973 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
1999 unsigned Immr = ShiftImm; local
2001 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
2037 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
2049 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
2053 return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imm
1837 isBitfieldExtractOpFromSExtInReg(SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms) argument
1916 isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, bool BiggerPattern) argument
2036 isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, unsigned NumberOfIgnoredLowBits = 0, bool BiggerPattern = false) argument
2078 unsigned Opc, Immr, Imms; local
[all...] |
| H A D | AArch64LoadStoreOptimizer.cpp | 1076 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
1077 int Imms = Immr + Width - 1;
1080 | ((Immr) << 6) // immr
1097 .addImm(Immr)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 252 // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
256 unsigned Immr = (Size - I) & (Size - 1); local
269 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
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