| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2203 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); local
2205 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2206 return ImmReg;
2223 unsigned ImmReg = createResultReg(RC); local
2224 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2226 return ImmReg;
2385 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); local
2387 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2388 return ImmReg;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1041 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
1042 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1049 .addReg(ImmReg)
1135 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); local
1136 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1143 .addReg(ImmReg)
|
| H A D | R600ISelLowering.cpp | 2159 unsigned ImmReg = R600::ALU_LITERAL_X; local
2166 ImmReg = R600::ZERO;
2168 ImmReg = R600::HALF;
2170 ImmReg = R600::ONE;
2178 ImmReg = R600::ZERO;
2180 ImmReg = R600::ONE_INT;
2189 if (ImmReg == R600::ALU_LITERAL_X) {
2198 Src = DAG.getRegister(ImmReg, MVT::i32);
|
| H A D | SIInstrInfo.cpp | 6143 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
6148 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6152 .addReg(ImmReg, RegState::Kill)
6162 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
6163 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6166 .addReg(ImmReg, RegState::Kill)
6172 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
6177 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6181 .addReg(ImmReg, RegState::Kill)
|
| H A D | AMDGPUInstructionSelector.cpp | 1763 Register ImmReg = MRI->createVirtualRegister(DstRC); local
1778 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg)
1782 .addReg(ImmReg);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 470 unsigned ImmReg = createResultReg(RC); local
472 TII.get(Opc), ImmReg)
474 return ImmReg;
486 unsigned ImmReg = createResultReg(RC); local
488 TII.get(Opc), ImmReg)
490 return ImmReg;
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4601 unsigned ImmReg = DstReg; local
4606 ImmReg = ATReg;
4609 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4613 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4631 unsigned ImmReg = DstReg; local
4654 ImmReg = ATReg;
4657 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4661 // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
4662 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcRe
4731 unsigned ImmReg = DstReg; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1485 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
1486 if (ImmReg) {
1487 HBS::replaceReg(DR, ImmReg, MRI);
1488 BT.put(ImmReg, DRC);
|