Searched refs:HiLHS (Results 1 - 4 of 4) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 668 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); local
671 MRI->setRegBank(HiLHS, *Bank);
674 Regs.push_back(HiLHS);
678 .addDef(HiLHS)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1407 SDValue LoLHS, HiLHS, LoRHS, HiRHS; local
1409 GetSplitVector(N->getOperand(0), LoLHS, HiLHS);
1412 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0);
1420 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode();
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| H A D | TargetLowering.cpp | 7757 SDValue HiLHS;
7763 HiLHS =
7772 HiLHS = DAG.getConstant(0, dl, VT);
7789 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
7792 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2956 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); local
2958 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
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