Searched refs:HexagonII (Results 1 - 24 of 24) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp91 case HexagonII::HSIG_None:
94 case HexagonII::HSIG_L1:
95 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
96 case HexagonII::HSIG_L2:
97 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
98 Gb == HexagonII::HSIG_A);
99 case HexagonII::HSIG_S1:
100 return (Gb == HexagonII
[all...]
H A DHexagonMCInstrInfo.cpp237 unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
238 return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
244 return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
245 HexagonII::AddrModeMask);
312 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
330 return ((F >> HexagonII::ExtentAlignPos) & HexagonII
[all...]
H A DHexagonShuffler.cpp199 if (Type != HexagonII::TypeALU32_2op &&
200 Type != HexagonII::TypeALU32_3op &&
201 Type != HexagonII::TypeALU32_ADDI) {
461 case HexagonII::TypeS_2op:
462 case HexagonII::TypeS_3op:
463 case HexagonII::TypeALU64:
465 case HexagonII::TypeJ:
468 case HexagonII::TypeCVI_VM_VP_LDU:
469 case HexagonII::TypeCVI_VM_LD:
470 case HexagonII
[all...]
H A DHexagonMCCompound.cpp78 // enum HexagonII::CompoundGroup
84 return HexagonII::HCG_None;
95 return HexagonII::HCG_None;
102 return HexagonII::HCG_A;
108 return HexagonII::HCG_None;
116 return HexagonII::HCG_A;
120 return HexagonII::HCG_None;
126 return HexagonII::HCG_A;
130 return HexagonII::HCG_None;
136 return HexagonII
[all...]
H A DHexagonMCChecker.cpp170 HexagonII::TypeCVI_VM_TMP_LD)
273 if (Type == HexagonII::TypeDUPLEX) {
280 Type != HexagonII::TypeALU32_2op && Type != HexagonII::TypeALU32_3op &&
281 Type != HexagonII::TypeALU32_ADDI && Type != HexagonII::TypeS_2op &&
282 Type != HexagonII::TypeS_3op &&
283 (Type != HexagonII::TypeALU64 || HexagonMCInstrInfo::isFloat(MCII, ID));
437 llvm::HexagonMCInstrInfo::getType(MCII, I) == HexagonII::TypeNCJ)) {
479 if (Mode == HexagonII
[all...]
H A DHexagonBaseInfo.h24 /// HexagonII - This namespace holds all of the target specific flags that
26 namespace HexagonII { namespace in namespace:llvm
280 } // end namespace HexagonII
H A DHexagonMCCodeEmitter.cpp347 return HexagonII::INST_PARSE_LOOP_END;
354 return HexagonII::INST_PARSE_LOOP_END;
359 return HexagonII::INST_PARSE_DUPLEX;
362 return HexagonII::INST_PARSE_PACKET_END;
363 return HexagonII::INST_PARSE_NOT_END;
427 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
469 if (InsnType == HexagonII::TypeEXTENDER) {
479 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
665 bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
782 HexagonMCInstrInfo::getType(MCII, MI) == HexagonII
[all...]
H A DHexagonAsmBackend.cpp542 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
543 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
545 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ &&
547 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMCInstLower.cpp49 switch (MO.getTargetFlags() & ~HexagonII::HMOTF_ConstExtended) {
53 case HexagonII::MO_PCREL:
56 case HexagonII::MO_GOT:
59 case HexagonII::MO_LO16:
62 case HexagonII::MO_HI16:
65 case HexagonII::MO_GPREL:
68 case HexagonII::MO_GDGOT:
71 case HexagonII::MO_GDPLT:
74 case HexagonII::MO_IE:
77 case HexagonII
[all...]
H A DHexagonDepITypes.h12 namespace HexagonII { namespace in namespace:llvm
H A DHexagonInstrInfo.cpp217 case HexagonII::HSIG_None:
220 case HexagonII::HSIG_L1:
221 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
222 case HexagonII::HSIG_L2:
223 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224 Gb == HexagonII::HSIG_A);
225 case HexagonII::HSIG_S1:
226 return (Gb == HexagonII
[all...]
H A DHexagonOptAddrMode.cpp138 if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
141 else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
327 case HexagonII::MemAccessSize::DoubleWordAccess:
330 case HexagonII::MemAccessSize::WordAccess:
333 case HexagonII::MemAccessSize::HalfWordAccess:
336 case HexagonII::MemAccessSize::ByteAccess:
359 HII->getAddrMode(*MI) != HexagonII::BaseImmOffset ||
495 if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
505 } else if (HII->getAddrMode(*OldMI) == HexagonII
[all...]
H A DHexagonSelectionDAGInfo.cpp48 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
H A DHexagonSubtarget.cpp187 return Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
188 Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM;
274 HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
287 HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
H A DHexagonConstExtenders.cpp878 unsigned AM = (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
880 case HexagonII::Absolute:
881 case HexagonII::AbsoluteSet:
882 case HexagonII::BaseLongOffset:
955 case HexagonII::BaseImmOffset:
1077 uint64_t F = (D.TSFlags >> HexagonII::MemAccessSizePos) &
1078 HexagonII::MemAccesSizeMask;
1079 uint8_t A = HexagonII::getMemAccessSizeInBytes(HexagonII
[all...]
H A DHexagonBranchRelaxation.cpp218 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
H A DHexagonInstrInfo.h437 HexagonII::CompoundGroup
451 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
H A DHexagonRDFOpt.cpp221 if (HII.getAddrMode(MI) != HexagonII::PostInc)
H A DHexagonISelLowering.cpp547 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
1112 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1138 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1217 HexagonII::MO_PCREL);
1223 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1241 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1250 HexagonII::MO_PCREL);
1303 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1344 HexagonII
[all...]
H A DHexagonVLIWPacketizer.cpp1135 if (TJ != HexagonII::TypeALU32_2op &&
1136 TJ != HexagonII::TypeALU32_3op &&
1137 TJ != HexagonII::TypeALU32_ADDI)
H A DHexagonCopyToCombine.cpp153 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
H A DHexagonFrameLowering.cpp2286 bool Bad = (AM != HexagonII::BaseImmOffset);
2511 assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
H A DHexagonISelDAGToDAG.cpp223 unsigned SizeBits = (F >> HexagonII::MemAccessSizePos) &
224 HexagonII::MemAccesSizeMask;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp303 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
304 HexagonII::INST_PARSE_LOOP_END) {
317 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
318 HexagonII::INST_PARSE_DUPLEX) {
409 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
410 HexagonII::INST_PARSE_PACKET_END)

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