/freebsd-13-stable/sys/arm64/rockchip/clk/ |
H A D | rk3399_cru.c | 63 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7), 64 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6), 65 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5), 66 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4), 67 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3), 68 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2), 69 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1), 70 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0), 74 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7), 75 GATE( [all...] |
H A D | rk3288_cru.c | 83 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro 94 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12), 95 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11), 96 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10), 97 GATE(0, "gpll_ddr", "gpll", 0, 9), 98 GATE(0, "dpll_ddr", "dpll", 0, 8), 99 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7), 100 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5), 101 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4), 102 GATE(ACLK_CP [all...] |
H A D | rk_cru.h | 48 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
|
/freebsd-13-stable/sys/arm64/nvidia/tegra210/ |
H A D | tegra210_clk_per.c | 74 #define GATE(_id, cname, plist, _idx) \ macro 312 GATE(ISPB, "ispb", "clk_m", L(3)), 313 GATE(RTC, "rtc", "clk_s", L(4)), 314 GATE(TIMER, "timer", "clk_m", L(5)), 315 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 316 GATE(UARTB, "uartb", "pc_uartb", L(7)), 317 GATE(GPIO, "gpio", "clk_m", L(8)), 318 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), 319 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), 320 GATE(SPDIF_I [all...] |
H A D | tegra210_car.c | 125 #define GATE(_id, cname, plist, o, s) \ macro 250 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 251 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 252 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21), 253 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29), 254 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
|
H A D | tegra210_clk_pll.c | 211 #define GATE(_id, cname, plist, o, s) \ macro 513 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22), 514 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23), 515 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
|
/freebsd-13-stable/sys/arm/nvidia/tegra124/ |
H A D | tegra124_clk_per.c | 79 #define GATE(_id, cname, plist, _idx) \ macro 217 /* GATE(CPU, "cpu", "clk_m", L(0)), */ 218 GATE(ISPB, "ispb", "clk_m", L(3)), 219 GATE(RTC, "rtc", "clk_s", L(4)), 220 GATE(TIMER, "timer", "clk_m", L(5)), 221 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 222 GATE(UARTB, "uartb", "pc_uartb", L(7)), 223 GATE(VFIR, "vfir", "pc_vfir", L(7)), 224 /* GATE(GPIO, "gpio", "clk_m", L(8)), */ 225 GATE(SDMMC [all...] |
H A D | tegra124_car.c | 124 #define GATE(_id, cname, plist, o, s) \ macro 259 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 260 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
|
/freebsd-13-stable/sys/arm64/freescale/imx/ |
H A D | imx8mq_ccm.c | 170 GATE(IMX8MQ_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x28, 21), 171 GATE(IMX8MQ_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x18, 21), 172 GATE(IMX8MQ_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x20, 21), 173 GATE(IMX8MQ_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x0, 21), 174 GATE(IMX8MQ_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x8, 21), 175 GATE(IMX8MQ_VIDEO_PLL1_OUT, "video_pll1_out", "video_pll1_bypass", 0x10, 21), 177 GATE(IMX8MQ_SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, 9), 178 GATE(IMX8MQ_SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, 11), 179 GATE(IMX8MQ_SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, 13), 180 GATE(IMX8MQ_SYS1_PLL_133M_C [all...] |
H A D | imx_ccm_clk.h | 123 #define GATE(_id, _name, _pname, _o, _shift) \ macro 154 /* Composite clock with GATE, MUX, PRE_DIV, and POST_DIV */
|
/freebsd-13-stable/sys/mips/ingenic/ |
H A D | jz4780_clock.c | 96 #define GATE(_id, cname, pname, bit) { \ macro 148 GATE(JZ4780_CLK_OTGPHY, "otg_phy", "ext", 0), 343 GATE(JZ4780_CLK_NEMC, "nemc", "ahb2", 0), 344 GATE(JZ4780_CLK_OTG0, "otg0", "ext", 2), 345 GATE(JZ4780_CLK_SSI0, "ssi0", "ssi", 4), 346 GATE(JZ4780_CLK_SMB0, "smb0", "pclk", 5), 347 GATE(JZ4780_CLK_SMB1, "smb1", "pclk", 6), 348 GATE(JZ4780_CLK_SCC, "scc", "ext", 7), 349 GATE(JZ4780_CLK_AIC, "aic", "ext", 8), 350 GATE(JZ4780_CLK_TSSI [all...] |