Searched refs:FalseReg (Results 1 - 18 of 18) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp715 Register FalseReg = local
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg);
722 FalseReg = FRIt->second;
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
H A DX86InstrInfo.h341 Register FalseReg) const override;
H A DX86InstrInfo.cpp3305 Register FalseReg, int &CondCycles,
3319 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3343 Register FalseReg) const {
3351 .addReg(FalseReg)
3302 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
531 // allocator ensure the FalseReg is allocated the same register as operand 0.
532 FalseReg.setImplicit();
533 NewMI.add(FalseReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h244 Register FalseReg) const override;
H A DSystemZInstrInfo.cpp536 Register FalseReg, int &CondCycles,
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
572 Register FalseReg) const {
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
594 FalseReg = FReg;
605 .addReg(FalseReg).addReg(TrueReg)
533 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Pred, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
H A DSystemZISelLowering.cpp7108 Register FalseReg = MI->getOperand(2).getReg(); local
7114 std::swap(TrueReg, FalseReg);
7119 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
7120 FalseReg = RegRewriteTable[FalseReg].second;
7125 .addReg(FalseReg).addMBB(FalseMBB);
7128 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
7213 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1097 Register FalseReg, int &CondCycles,
1110 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1136 Register FalseReg) const {
1143 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1144 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1195 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1196 SecondReg = SwapOps ? TrueReg : FalseReg;
2457 unsigned TrueReg, unsigned FalseReg,
2464 return Imm1 < Imm2 ? TrueReg : FalseReg;
2466 return Imm1 > Imm2 ? TrueReg : FalseReg;
1094 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
[all...]
H A DPPCInstrInfo.h396 Register FalseReg) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp790 auto FalseReg = MIB.getReg(3); local
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
797 .addUse(FalseReg)
H A DARMBaseInstrInfo.cpp2305 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2307 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2335 // The tie makes the register allocator ensure the FalseReg is allocated the
2337 FalseReg.setImplicit();
2338 NewMI.add(FalseReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp929 Register FalseReg) const {
944 .addReg(FalseReg)
959 .addReg(FalseReg)
973 .addReg(FalseReg)
987 .addReg(FalseReg)
1003 .addReg(FalseReg)
1019 .addReg(FalseReg)
1037 .addReg(FalseReg)
2333 Register FalseReg, int &CondCycles,
2340 assert(MRI.getRegClass(FalseReg)
2330 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h205 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp528 Register FalseReg, int &CondCycles,
534 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
556 else if (canFoldIntoCSel(MRI, FalseReg))
578 Register TrueReg, Register FalseReg) const {
684 // FalseReg, so we need to invert the condition.
686 TrueReg = FalseReg;
688 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
692 FalseReg = NewVReg;
701 MRI.constrainRegClass(FalseReg, RC);
706 .addReg(FalseReg)
525 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp890 unsigned FalseReg = getRegForValue(Select->getFalseValue()); local
891 if (FalseReg == 0)
895 std::swap(TrueReg, FalseReg);
930 .addReg(FalseReg)
H A DWebAssemblyISelLowering.cpp369 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; local
374 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
407 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
411 .addReg(FalseReg)
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h828 /// instruction that chooses between TrueReg and FalseReg based on the
832 /// FalseReg, and Cond to the destination register. In most cases, a select
841 /// @param FalseReg Virtual register to select when Cond is false.
844 /// @param FalseCycles Latency from FalseReg to select output.
847 Register TrueReg, Register FalseReg,
854 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
867 /// @param FalseReg Virtual register to copy when Cons is false.
871 Register TrueReg, Register FalseReg) const {
845 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument

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