| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 391 bool isRegOffOpcode(unsigned ExtOpc) const ;
392 unsigned getRegOffOpcode(unsigned ExtOpc) const;
393 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
866 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const {
868 // that corresponds to the ExtOpc, return it, otherwise return 0.
870 switch (ExtOpc) {
875 const MCInstrDesc &D = HII->get(ExtOpc);
883 switch (ExtOpc) {
956 if (!isStoreImmediate(ExtOpc))
957 return ExtOpc;
1608 unsigned ExtOpc = MI.getOpcode(); local
1726 unsigned ExtOpc = MI.getOpcode(); local
[all...] |
| H A D | HexagonBitSimplify.cpp | 2513 unsigned ExtOpc = 0;
2516 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb;
2518 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth;
2520 ExtOpc = Hexagon::A2_andir;
2522 if (ExtOpc == 0) {
2523 ExtOpc =
2535 if (!validateReg({R,SR}, ExtOpc, 1))
2539 if (MI->getOpcode() == ExtOpc) {
2540 // All possible ExtOpc's have the source in operand(1).
2551 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), New
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 406 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, argument
409 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
410 TargetOpcode::G_SEXT == ExtOpc) &&
420 Opcode = ExtOpc;
|
| H A D | LegalizerHelper.cpp | 1954 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( local
1956 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1957 ExtOpc == TargetOpcode::G_ANYEXT) &&
1960 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
|
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 696 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
705 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1893 unsigned ExtOpc,
1896 if (ExtOpc == AMDGPU::G_ZEXT) {
1898 } else if (ExtOpc == AMDGPU::G_SEXT) {
1910 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension");
1891 extendLow32IntoHigh32(MachineIRBuilder &B, Register Hi32Reg, Register Lo32Reg, unsigned ExtOpc, const RegisterBank &RegBank, bool IsBooleanSrc = false) argument
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1208 unsigned ExtOpc = local
1210 return DAG.getNode(ExtOpc, DL, PVT, Op);
9576 unsigned ExtOpc,
9590 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
9592 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
9914 ISD::NodeType ExtOpc) {
9925 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI);
9935 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc);
9954 ISD::NodeType ExtOpc) {
9969 SDValue PassThru = DAG.getNode(ExtOpc, d
9575 ExtendUsesToFormExtLoad(EVT VT, SDNode *N, SDValue N0, unsigned ExtOpc, SmallVectorImpl<SDNode *> &ExtendNodes, const TargetLowering &TLI) argument
9910 tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
9950 tryToFoldExtOfMaskedLoad(SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
[all...] |
| H A D | TargetLowering.cpp | 4366 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) local
4368 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue()
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20260 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In,
20267 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo);
20268 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi);
23357 unsigned ExtOpc =
23360 return DAG.getNode(ExtOpc, dl, VT, In);
[all...] |