Searched refs:ExecReg (Results 1 - 5 of 5) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp70 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; local
81 if (A->modifiesRegister(ExecReg, TRI))
96 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
100 if (Op1.getReg() != ExecReg)
144 if (SReg == ExecReg) {
H A DSIOptimizeExecMaskingPreRA.cpp106 const unsigned ExecReg = Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; local
124 if (CmpReg == ExecReg) {
128 } else if (And->getOperand(2).getReg() != ExecReg) {
169 .addReg(ExecReg)
H A DSILowerI1Copies.cpp62 unsigned ExecReg; member in class:__anon3982::SILowerI1Copies
470 ExecReg = AMDGPU::EXEC_LO;
478 ExecReg = AMDGPU::EXEC;
832 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
835 .addReg(ExecReg)
850 .addReg(ExecReg);
861 .addReg(ExecReg);
874 .addReg(ExecReg);
878 .addReg(CurMaskedReg ? CurMaskedReg : ExecReg);
H A DSIRegisterInfo.cpp905 Register ExecReg = OnlyExecLo ? AMDGPU::EXEC_LO : AMDGPU::EXEC; local
924 BuildMI(*MBB, MI, DL, TII->get(ExecMovOpc), SavedExecReg).addReg(ExecReg);
927 BuildMI(*MBB, MI, DL, TII->get(ExecMovOpc), ExecReg).addImm(VGPRLanes);
960 BuildMI(*MBB, MI, DL, TII->get(ExecMovOpc), ExecReg)
H A DAMDGPURegisterBankInfo.cpp744 const unsigned ExecReg = Subtarget.isWave32() ? local
1012 .addDef(ExecReg)
1013 .addReg(ExecReg)
1025 .addReg(ExecReg);
1030 .addDef(ExecReg)

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