Searched refs:DestSub1 (Results 1 - 3 of 3) sorted by relevance
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 1668 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 1679 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) 1693 .addReg(DestSub1)
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H A D | SIInstrInfo.cpp | 5798 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); local 5799 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); 5805 .addReg(DestSub1) 5831 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 5868 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) 5878 .addReg(DestSub1) 5935 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); local 5936 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) 5944 .addReg(DestSub1)
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H A D | SIISelLowering.cpp | 3783 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); local 3800 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1); 3804 .addReg(DestSub1) 3821 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 3861 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) 3871 .addReg(DestSub1)
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Completed in 202 milliseconds