Searched refs:DestSub0 (Results 1 - 3 of 3) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1667 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
1670 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_I32_e64), DestSub0)
1691 .addReg(DestSub0)
H A DSIInstrInfo.cpp5792 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); local
5793 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
5803 .addReg(DestSub0)
5830 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
5860 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
5876 .addReg(DestSub0)
5930 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); local
5931 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
5942 .addReg(DestSub0)
H A DSIISelLowering.cpp3782 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); local
3799 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
3802 .addReg(DestSub0)
3820 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local
3853 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3869 .addReg(DestSub0)

Completed in 302 milliseconds