Searched refs:DefInstr (Results 1 - 4 of 4) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCombiner.cpp146 MachineInstr *DefInstr = nullptr; local
149 DefInstr = MRI->getUniqueVRegDef(MO.getReg());
151 if (DefInstr && DefInstr->isPHI())
152 DefInstr = nullptr;
153 return DefInstr;
190 MachineInstr *DefInstr = InsInstrs[II->second]; local
191 assert(DefInstr &&
194 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
196 LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefId
199 MachineInstr *DefInstr = getOperandDef(MO); local
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H A DLiveRangeShrink.cpp199 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); local
200 if (!DefInstr.isCopy())
202 Insert = FindDominatedInstruction(DefInstr, Insert, IOM);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp346 MachineInstr *DefInstr, const MachineRegisterInfo *MRI,
350 MachineInstr *DefInstr,
694 MachineInstr *DefInstr,
721 if ((&(*MII)) == DefInstr) {
734 MachineInstr *DefInstr,
1979 MachineInstr *DefInstr = getDefInstr(SourceReg);
1980 if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) {
1989 storePHILinearizationInfoDest(DestReg, *DefInstr);
1993 DefInstr
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H A DSIPeepholeSDWA.cpp317 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg());
318 if (!DefInstr)
321 for (auto &DefMO : DefInstr->defs()) {

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