Searched refs:AssignedReg (Results 1 - 7 of 7) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 99 Register AssignedReg;
101 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
127 if (AssignedReg) {
128 for (; *I != AssignedReg; ++I)
129 assert(I != RC->end() && "AssignedReg should be a member of provided RC");
132 // Finally, assign the registers. If the AssignedReg isn't set, create virtual
136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 612 unsigned AssignedReg = FuncInfo.ValueMap[I]; local
614 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1177 unsigned AssignedReg = FuncInfo.ValueMap[I]; local
1179 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1283 unsigned AssignedReg = FuncInfo.ValueMap[I]; local
1285 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1921 unsigned AssignedReg local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 754 Register AssignedReg;
756 std::tie(AssignedReg, RC) = TLI->getRegForInlineAsmConstraint(
758 if (AssignedReg) {
761 RC = TRI->getPhysRegClass(AssignedReg);
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| H A D | SIISelLowering.cpp | 11675 unsigned AssignedReg; local
11677 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint(
11681 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 225 MCPhysReg AssignedReg, bool Kill);
313 /// Insert spill instruction for \p AssignedReg before \p Before. Update
316 MCPhysReg AssignedReg, bool Kill) {
318 << " in " << printReg(AssignedReg, TRI));
323 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI);
315 spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill) argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 506 Register &AssignedReg = FuncInfo.ValueMap[I]; local
507 if (!AssignedReg)
509 AssignedReg = Reg;
510 else if (Reg != AssignedReg) {
511 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
513 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
517 AssignedReg = Reg;
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| H A D | SelectionDAGBuilder.cpp | 7925 unsigned AssignedReg; local
7927 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
7998 if (AssignedReg) {
7999 for (; *I != AssignedReg; ++I)
8000 assert(I != RC->end() && "AssignedReg should be member of RC");
8005 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
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