/freebsd-12-stable/sys/arm/include/ |
H A D | sysreg.h | 63 #define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 64 #define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 65 #define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 66 #define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 67 #define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 68 #define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 70 #define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 71 #define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 72 #define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 73 #define CP15_ID_AFR0(rr) p15, [all...] |
H A D | asmacros.h | 42 mrc p15, 0, tmp, c13, c0, 4
|
/freebsd-12-stable/sys/arm/arm/ |
H A D | cpufunc_asm_arm9.S | 41 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 42 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 60 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 61 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ 62 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
|
H A D | cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 52 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 65 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 71 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
|
H A D | cpufunc_asm_pj4b.S | 43 mrc p15, 1, r0, c15, c1, 0 48 mcr p15, 1, r0, c15, c1, 0 51 mrc p15, 1, r0, c15, c1, 1 58 mcr p15, 1, r0, c15, c1, 1 61 mrc p15, 1, r0, c15, c2, 0 67 mcr p15, 1, r0, c15, c2, 0 70 mrc p15, 1, r0, c15, c1, 2 77 mcr p15, 1, r0, c15, c1, 2 80 mrc p15, 0, r0, c1, c0, 1 82 mcr p15, [all...] |
H A D | cpufunc_asm.S | 66 mcr p15, 0, r0, c3, c0, 0 106 mrc p15, 0, r2, c2, c0, 0; \ 111 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 113 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 115 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 116 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 119 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 120 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
|
H A D | cpufunc_asm_armv5_ec.S | 61 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 62 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ 64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 66 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 68 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 102 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 107 mrc p15, [all...] |
H A D | cpufunc_asm_arm11x6.S | 81 mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */ 82 mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
H A D | cpufunc_asm_sheeva.S | 51 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ 52 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ 55 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ 56 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ 61 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 63 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 65 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 94 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ 95 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ 107 mcr p15, [all...] |
H A D | swtch-v4.S | 154 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 281 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 290 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 320 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
|
H A D | locore-v4.S | 51 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 216 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 217 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 221 mcr p15, 0, r0, c3, c0, 0 411 mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
|
H A D | copystr.S | 53 mrc p15, 0, tmp, c13, c0, 4; \
|
H A D | fusu.S | 45 mrc p15, 0, tmp, c13, c0, 4; \
|
H A D | bcopyinout.S | 59 mrc p15, 0, tmp, c13, c0, 4; \
|
H A D | bcopyinout_xscale.S | 47 mrc p15, 0, tmp, c13, c0, 4; \
|
/freebsd-12-stable/lib/libc/arm/gen/ |
H A D | __aeabi_read_tp.S | 38 mrc p15, 0, r0, c13, c0, 3
|
/freebsd-12-stable/sys/arm/mv/armadaxp/ |
H A D | mptramp.S | 36 mcr p15, 0, r0, c7, c7, 0 43 mrc p15, 0, r0, c0, c0, 5
|
/freebsd-12-stable/stand/arm/uboot/ |
H A D | start.S | 43 mrc p15, 0, ip, c1, c0, 0 46 mcr p15, 0, ip, c1, c0, 0
|
/freebsd-12-stable/secure/lib/libcrypto/arm/ |
H A D | armv4cpuid.S | 136 mrrc p15,0,r0,r1,c14 @ CNTPCT 138 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
/freebsd-12-stable/crypto/openssl/crypto/ |
H A D | armv4cpuid.pl | 155 mrrc p15,0,r0,r1,c14 @ CNTPCT 157 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
/freebsd-12-stable/crypto/openssl/crypto/bn/asm/ |
H A D | ia64-mont.pl | 448 cmp4.le p14,p15=8,in5 } 483 (p15)fcvt.fxu ai7=f0 489 (p15)fcvt.fxu bj[0]=f0 495 (p15)fcvt.fxu ni7=f0 839 (p15)br.cond.dpnt.few .Ldone };;
|
H A D | ia64.S | 1535 pred=p15
|
/freebsd-12-stable/usr.sbin/pc-sysinstall/backend/ |
H A D | functions-disk.sh | 526 p1|p2|p3|p4|p5|p6|p7|p8|p9|p10|p11|p12|p13|p14|p15|p16|p17|p18|p19|p20)
|
/freebsd-12-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-ia64.pl | 188 cmp.eq p15,p0=7,r8 };; 235 (p15) br.cond.dpnt.many .L7byte };;
|
/freebsd-12-stable/sys/contrib/alpine-hal/eth/ |
H A D | al_hal_eth_ec_regs.h | 155 uint32_t p15; member in struct:al_ec_epe_res 1424 /**** p15 register ****/
|