Searched refs:mmio_base (Results 1 - 9 of 9) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/i915/
H A Dintel_ringbuffer.h24 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
25 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
27 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
28 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
30 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
31 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
33 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
34 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
36 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
37 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), va
51 u32 mmio_base; member in struct:intel_ring_buffer
[all...]
H A Dintel_ringbuffer.c356 RING_ACTHD(ring->mmio_base) : ACTHD;
873 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
875 mmio = RING_HWS_PGA(ring->mmio_base);
1492 POSTING_READ(RING_TAIL(ring->mmio_base));
1608 ring->mmio_base = RENDER_RING_BASE;
1694 ring->mmio_base = RENDER_RING_BASE;
1764 ring->mmio_base = GEN6_BSD_RING_BASE;
1782 ring->mmio_base = BSD_RING_BASE;
1810 ring->mmio_base = BLT_RING_BASE;
H A Di915_irq.c1130 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1133 = I915_READ(RING_SYNC_0(ring->mmio_base));
1135 = I915_READ(RING_SYNC_1(ring->mmio_base));
1141 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1142 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1143 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1144 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1145 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1158 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
H A Di915_reg.h120 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
121 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
122 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
547 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
H A Dintel_pm.c2573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
/freebsd-12-stable/sys/dev/drm/
H A Dsavage_bci.c566 unsigned long mmio_base, fb_base, fb_size, aperture_base; local
581 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
609 mmio_base = drm_get_resource_start(dev, 0);
629 mmio_base = drm_get_resource_start(dev, 0);
638 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
H A Dmga_dma.c414 dev_priv->mmio_base = drm_get_resource_start(dev, 1);
723 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
H A Dmga_drv.h119 u32 mmio_base; /**< Bus address of base of MMIO. */ member in struct:drm_mga_private
/freebsd-12-stable/sys/dev/hyperv/pcib/
H A Dvmbus_pcib.c282 uint64_t mmio_base; member in struct:pci_bus_d0_entry
1121 d0_entry->mmio_base = rman_get_start(hbus->cfg_res);

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