/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMachineFunctionInfo.cpp | 56 return LiveIn.second.isZExt();
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H A D | PPCFastISel.cpp | 163 bool isZExt, unsigned DestReg,
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H A D | PPCISelLowering.cpp | 3752 else if (Flags.isZExt()) 6996 else if (Flags.isZExt())
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineFrameInfo.h | 177 bool isZExt = false; member in struct:llvm::MachineFrameInfo::StackObject 502 return Objects[ObjectIdx+NumFixedObjects].isZExt; 508 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt;
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H A D | TargetCallingConv.h | 68 bool isZExt() const { return IsZExt; } function in struct:llvm::ISD::ArgFlagsTy
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 194 bool isZExt); 196 unsigned Alignment = 0, bool isZExt = true, 205 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 917 unsigned Alignment, bool isZExt, bool allocReg) { 929 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; 931 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; 933 if (isZExt) { 948 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; 950 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; 952 Opc = isZExt 916 ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument 1350 ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, bool isZExt) argument 2603 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument 2749 bool isZExt = isa<ZExtInst>(I); local 2899 uint8_t isZExt : 1; member in struct:FoldableLoadExtendsStruct 2929 bool isZExt; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 1214 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); 1222 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); 1759 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { 1760 bool IsZExt = Outs[0].Flags.isZExt(); 1809 bool isZExt = isa<ZExtInst>(I); local 1826 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) 1912 bool isZExt) { 1914 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); 1911 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
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H A D | MipsCallLowering.cpp | 391 if (Flags.isZExt())
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H A D | MipsISelLowering.cpp | 2878 else if (ArgFlags.isZExt()) 2890 else if (ArgFlags.isZExt())
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 234 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt); 2405 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*isZExt=*/true); 2926 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); 3094 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); 3104 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); 3918 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 3921 bool IsZExt = Outs[0].Flags.isZExt(); 4329 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false); 5009 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 384 else if (ArgFlags.isZExt())
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 509 else if (ArgFlags.isZExt())
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1229 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 1240 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
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H A D | X86ISelLowering.cpp | 4454 if (Flags.isZExt() != MFI.isObjectZExt(FI) || [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1453 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && 1455 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
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