Searched refs:constrainRegClass (Results 1 - 25 of 34) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp373 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass);
376 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_YRegClass);
379 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_ZRegClass);
382 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_WRegClass);
H A DSILowerI1Copies.cpp487 MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, function
85 MachineRegisterInfo::constrainRegClass(unsigned Reg, function in class:MachineRegisterInfo
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
109 if (!::constrainRegClass(
H A DOptimizePHIs.cpp181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
H A DMachineLoopUtils.cpp68 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
H A DUnreachableBlockElim.cpp187 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
H A DTargetInstrInfo.cpp816 MRI.constrainRegClass(RegA, RC);
818 MRI.constrainRegClass(RegB, RC);
820 MRI.constrainRegClass(RegX, RC);
822 MRI.constrainRegClass(RegY, RC);
824 MRI.constrainRegClass(RegC, RC);
H A DTailDuplicator.cpp248 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
425 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC);
H A DModuloSchedule.cpp1184 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
1231 MRI.constrainRegClass(MI.getOperand(1).getReg(),
1476 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue()));
1486 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg));
H A DTwoAddressInstructionPass.cpp1488 MRI->constrainRegClass(DstReg, RC);
1601 MRI->constrainRegClass(RegA, RC);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp643 MRI->constrainRegClass(HeadCond[2].getReg(),
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
H A DAArch64InstrInfo.cpp580 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
586 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
626 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
630 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
634 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
637 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
665 MRI.constrainRegClass(TrueReg, RC);
666 MRI.constrainRegClass(FalseReg, RC);
1079 !MRI->constrainRegClass(Reg, OpRegCstraints))
2870 MF.getRegInfo().constrainRegClass(SrcRe
[all...]
H A DAArch64RegisterInfo.cpp420 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp237 if (!MRI.constrainRegClass(KilledProdReg,
H A DPPCRegisterInfo.cpp1264 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1290 MRI.constrainRegClass(BaseReg,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp164 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
205 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
668 if (!MRI->constrainRegClass(FrameReg, RegClass))
H A DA15SDOptimizer.cpp641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
H A DARMBaseRegisterInfo.cpp646 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
H A DARMLoadStoreOptimizer.cpp2331 MRI->constrainRegClass(FirstReg, TRC);
2332 MRI->constrainRegClass(SecondReg, TRC);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
457 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
H A DFastISel.cpp2043 if (!MRI.constrainRegClass(Op, RegClass)) {
2251 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp135 // If the register already has a class, fallback to MRI::constrainRegClass.
138 return MRI.constrainRegClass(Reg, &RC);
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h580 /// constrainRegClass(ToReg, getRegClass(FromReg))
680 /// constrainRegClass - Constrain the register class of the specified virtual
691 const TargetRegisterClass *constrainRegClass(unsigned Reg,
703 /// \note Use this method instead of constrainRegClass and
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp509 if (!MRI.constrainRegClass(DestReg, PreviousClass))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp1029 MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass);

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