Searched refs:cfg1 (Results 1 - 23 of 23) sorted by relevance

/freebsd-12-stable/sys/dev/bhnd/nvram/
H A Dbhnd_nvram_data_bcmreg.h60 #define BCM_NVRAM_CFG1_SDRAM_CFG_FIELD cfg1
66 #define BCM_NVRAM_CFG1_SDRAM_REFRESH_FIELD cfg1
H A Dbhnd_nvram_data_bcmvar.h68 uint32_t cfg1; /**< sdram_config:16, sdram_refresh:16 */ member in struct:bhnd_nvram_bcmhdr
H A Dbhnd_nvram_data_bcm.c434 .cfg1 = 0,
443 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_CFG,
445 hdr.cfg1 = BCM_NVRAM_SET_BITS(hdr.cfg1, BCM_NVRAM_CFG1_SDRAM_REFRESH,
/freebsd-12-stable/sys/mips/mips/
H A Dcpu.c150 u_int32_t cfg1; local
178 cfg1 = mips_rd_config1();
183 if (cfg1 & MIPS_CONFIG1_M) {
190 if (cfg1 & MIPS_CONFIG1_FP)
227 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
240 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT;
243 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1;
245 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
254 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
258 (((cfg1
351 uint32_t cfg0, cfg1, cfg2, cfg3; local
[all...]
/freebsd-12-stable/sys/mips/atheros/ar531x/
H A Dar5312_chip.c122 uint32_t cfg0, cfg1; local
127 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
129 bank0 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK0);
130 bank1 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK1);
138 printf("SDRMCTL %x %x %x %x\n", cfg0, cfg1, size0, size1);
/freebsd-12-stable/sys/dev/ata/chipsets/
H A Data-highpoint.c98 if (idx->cfg1 == HPT_374) {
132 if (ctlr->chip->cfg1 < HPT_372)
155 if (ctlr->chip->cfg1 == HPT_366)
195 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
207 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) {
H A Data-amd.c99 if (ctlr->chip->cfg1 & AMD_BUG)
124 if (ctlr->chip->cfg1 & AMD_CABLE) {
154 if (ctlr->chip->cfg1 & AMD_CABLE)
H A Data-sis.c126 id[0].cfg1 = SIS_133NEW;
140 id[0].cfg1 = SIS_133OLD;
143 id[0].cfg1 = SIS_100NEW;
170 switch (ctlr->chip->cfg1) {
250 if (ctlr->chip->cfg1 == SIS_133NEW) {
264 switch (ctlr->chip->cfg1) {
H A Data-nvidia.c181 if ((ctlr->chip->cfg1 & NVAHCI) &&
198 if (ctlr->chip->cfg1 & NVAHCI) {
209 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
219 if (ctlr->chip->cfg1 & NVQ) {
288 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
289 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
293 if (ctlr->chip->cfg1 & NVQ)
303 if (ctlr->chip->cfg1 & NVQ)
H A Data-serverworks.c134 if (ctlr->chip->cfg1 == SWKS_MIO) {
149 else if (ctlr->chip->cfg1 == SWKS_33) {
168 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1);
361 if (ctlr->chip->cfg1 != SWKS_33) {
H A Data-ati.c106 switch (ctlr->chip->cfg1) {
137 if (ctlr->chip->cfg1 == ATI_AHCI) {
H A Data-intel.c268 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
290 (ctlr->chip->cfg1 & INTEL_ICH5))
337 if (ctlr->chip->cfg1 & INTEL_ICH5) {
353 } else if (ctlr->chip->cfg1 & INTEL_6CH2) {
375 if ((ctlr->chip->cfg1 & INTEL_ICH5)) {
379 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
432 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2))
H A Data-jmicron.c117 if (ctlr->chip->cfg1) {
H A Data-marvell.c130 if (ctlr->chip->cfg1) {
H A Data-via.c251 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
253 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
255 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
365 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
H A Data-acard.c101 if (ctlr->chip->cfg1 == ATP_OLD) {
H A Data-promise.c226 switch (ctlr->chip->cfg1) {
377 if (ctlr->chip->cfg1 == PR_NEW) {
482 switch (ctlr->chip->cfg1) {
513 if (ctlr->chip->cfg1 < PR_TX)
515 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
H A Data-acerlabs.c116 ctlr->channels = ctlr->chip->cfg1;
H A Data-siliconimage.c113 switch (ctlr->chip->cfg1) {
/freebsd-12-stable/sys/dev/qlnx/qlnxe/
H A Dspad_layout.h209 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
H A Dnvm_cfg.h2032 struct nvm_cfg1 cfg1; member in struct:nvm_cfg
/freebsd-12-stable/sys/dev/et/
H A Dif_et.c511 uint32_t cfg1, cfg2, ctrl; local
544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
545 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
576 cfg1 |= ET_MAC_CFG1_TXFLOW;
579 cfg1 |= ET_MAC_CFG1_RXFLOW;
585 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
586 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1);
591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
592 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
/freebsd-12-stable/sys/dev/ata/
H A Data-pci.h35 int cfg1; member in struct:ata_chip_id

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