Searched refs:Zero32 (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp346 Value *Zero32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0); local
364 Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp1653 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass); local
1655 Zero32);
1663 .addReg(Zero32, 0, X86::sub_16bit);
1667 .addReg(Zero32);
1672 .addReg(Zero32)
H A DX86FastISel.cpp1952 unsigned Zero32 = createResultReg(&X86::GR32RegClass); local
1954 TII.get(X86::MOV32r0), Zero32);
1962 .addReg(Zero32, 0, X86::sub_16bit);
1966 .addReg(Zero32);
1970 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DGCOVProfiling.cpp1028 Constant *Zero32 = Builder.getInt32(0);
1030 Constant *TwoZero32s[] = {Zero32, Zero32};
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1456 const auto Zero32 = B.buildConstant(S32, 0);
1459 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
1466 auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp3858 auto Zero32 = MIRBuilder.buildConstant(S32, 0); local
3867 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3887 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);

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