| /freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_AArch64.S | 23 STP X5, X6, [SP, #-16]!
48 LDP X5, X6, [SP], #16
70 STP X5, X6, [SP, #-16]!
88 LDP X5, X6, [SP], #16
110 STP X5, X6, [SP, #-16]!
139 LDP X5, X6, [SP], #16
|
| /freebsd-12-stable/contrib/libstdc++/include/ext/ |
| H A D | typelist.h | 318 #define _GLIBCXX_TYPELIST_CHAIN6(X0, X1, X2, X3, X4, X5) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN5(X1, X2, X3, X4, X5) >
319 #define _GLIBCXX_TYPELIST_CHAIN7(X0, X1, X2, X3, X4, X5, X6) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN6(X1, X2, X3, X4, X5, X6) >
320 #define _GLIBCXX_TYPELIST_CHAIN8(X0, X1, X2, X3, X4, X5, X6, X7) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN7(X1, X2, X3, X4, X5, X6, X7) >
321 #define _GLIBCXX_TYPELIST_CHAIN9(X0, X1, X2, X3, X4, X5, X6, X7, X8) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN8(X1, X2, X3, X4, X5, X6, X7, X8) >
322 #define _GLIBCXX_TYPELIST_CHAIN10(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN9(X1, X2, X3, X4, X5, X
[all...] |
| /freebsd-12-stable/sys/crypto/skein/ |
| H A D | skein_block.c | 268 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ local
273 Xptr[4] = &X4; Xptr[5] = &X5; Xptr[6] = &X6; Xptr[7] = &X7;
306 X5 = w[5] + ks[5] + ts[0];
331 X5 += ks[((R)+6) % 9] + ts[((R)+1) % 3]; \
346 X5 += ks[r+(R)+5] + ts[r+(R)+0]; \
425 ctx->X[5] = X5 ^ w[5];
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 671 // First we need to filter out candidates where the X5 register (IE t0) can't
678 return !LRU.available(RISCV::X5);
742 // Don't allow modifying the X5 register which we use for return addresses for
744 if (MI.modifiesRegister(RISCV::X5, TRI) ||
745 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
783 .addReg(RISCV::X5)
793 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
|
| H A D | RISCVFrameLowering.cpp | 375 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
|
| H A D | RISCVISelLowering.cpp | 1860 // X5 and X6 might be used for save-restore libcall.
2627 .Case("{t0}", RISCV::X5)
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 24 AArch64::X3, AArch64::X4, AArch64::X5,
|
| H A D | AArch64FastISel.cpp | 3010 AArch64::X5, AArch64::X6, AArch64::X7 },
|
| H A D | AArch64ISelLowering.cpp | 3600 AArch64::X3, AArch64::X4, AArch64::X5,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 36 case AArch64::X5: return AArch64::W5;
76 case AArch64::W5: return AArch64::X5;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 102 {codeview::RegisterId::ARM64_X5, AArch64::X5},
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 419 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3782 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4197 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4620 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5880 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6612 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6904 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
|