Searched refs:X4 (Results 1 - 22 of 22) sorted by relevance

/freebsd-12-stable/crypto/openssl/crypto/seed/
H A Dseed_local.h57 # define KEYSCHEDULE_UPDATE0(T0, T1, X1, X2, X3, X4, KC) \
59 (X3) = (((X3)<<8) ^ ((X4)>>24)) & 0xffffffff; \
60 (X4) = (((X4)<<8) ^ ((T0)>>24)) & 0xffffffff; \
62 (T1) = ((X2) + (KC) - (X4)) & 0xffffffff
64 # define KEYSCHEDULE_UPDATE1(T0, T1, X1, X2, X3, X4, KC) \
69 (T1) = ((X2) + (KC) - (X4)) & 0xffffffff
99 # define E_SEED(T0, T1, X1, X2, X3, X4, rbase) \
101 (T1) = (X4) ^ (ks->data)[(rbase)+1]; \
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S22 STP X3, X4, [SP, #-16]!
49 LDP X3, X4, [SP], #16
69 STP X3, X4, [SP, #-16]!
89 LDP X3, X4, [SP], #16
109 STP X3, X4, [SP, #-16]!
140 LDP X3, X4, [SP], #16
/freebsd-12-stable/contrib/libstdc++/include/ext/
H A Dtypelist.h317 #define _GLIBCXX_TYPELIST_CHAIN5(X0, X1, X2, X3, X4) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN4(X1, X2, X3, X4) >
318 #define _GLIBCXX_TYPELIST_CHAIN6(X0, X1, X2, X3, X4, X5) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN5(X1, X2, X3, X4, X5) >
319 #define _GLIBCXX_TYPELIST_CHAIN7(X0, X1, X2, X3, X4, X5, X6) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN6(X1, X2, X3, X4, X5, X6) >
320 #define _GLIBCXX_TYPELIST_CHAIN8(X0, X1, X2, X3, X4, X5, X6, X7) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN7(X1, X2, X3, X4, X5, X6, X7) >
321 #define _GLIBCXX_TYPELIST_CHAIN9(X0, X1, X2, X3, X4, X5, X6, X7, X8) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN8(X1, X2, X3, X4, X
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/freebsd-12-stable/lib/libc/sparc64/fpu/
H A Dfpu.c101 #define X4(x) x,x,x,x macro
102 #define X8(x) X4(x),X4(x)
108 X4(FSR_UF),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp82 markSuperRegs(Reserved, RISCV::X4); // tp
H A DRISCVISelLowering.cpp544 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
560 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
2626 .Case("{tp}", RISCV::X4)
/freebsd-12-stable/sys/crypto/skein/
H A Dskein_block.c268 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ local
273 Xptr[4] = &X4; Xptr[5] = &X5; Xptr[6] = &X6; Xptr[7] = &X7;
305 X4 = w[4] + ks[4];
330 X4 += ks[((R)+5) % 9]; \
345 X4 += ks[r+(R)+4]; \
424 ctx->X[4] = X4 ^ w[4];
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp24 AArch64::X3, AArch64::X4, AArch64::X5,
H A DAArch64FastISel.cpp3009 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
H A DAArch64ISelLowering.cpp3600 AArch64::X3, AArch64::X4, AArch64::X5,
/freebsd-12-stable/sys/dev/mlx5/mlx5_core/
H A Dfs_core.h49 FS_FT_FDB = 0X4,
/freebsd-12-stable/sys/crypto/aesni/
H A Daesni_ghash.c164 __m128i X1, __m128i X2, __m128i X3, __m128i X4, __m128i *res)
176 H4_X4_lo = _mm_clmulepi64_si128(H4, X4, 0x00);
185 H4_X4_hi = _mm_clmulepi64_si128(H4, X4, 0x11);
204 tmp7 = _mm_shuffle_epi32(X4, 78);
206 tmp7 = _mm_xor_si128(tmp7, X4);
163 reduce4(__m128i H1, __m128i H2, __m128i H3, __m128i H4, __m128i X1, __m128i X2, __m128i X3, __m128i X4, __m128i *res) argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h35 case AArch64::X4: return AArch64::W4;
75 case AArch64::W4: return AArch64::X4;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp145 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp101 {codeview::RegisterId::ARM64_X4, AArch64::X4},
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp951 CASE_VSHUF(32X4, r)
956 CASE_VSHUF(32X4, m)
/freebsd-12-stable/contrib/gcc/config/ia64/
H A Dunwind-ia64.c1147 UNW_DEC_RESTORE_P(X4, qp, t, abreg, arg);
1149 UNW_DEC_SPILL_REG_P(X4, qp, t, abreg, x, ytreg, arg);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1783 if (Inst.getOperand(2).getReg() != RISCV::X4) {
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp1925 Value *X1, *X2, *X3, *X4; local
1927 match(OrOp1, m_OneUse(m_Xor(m_Value(X3), m_Value(X4))))) {
1928 // ((X1 ^ X2) || (X3 ^ X4)) == 0 --> (X1 == X2) && (X3 == X4)
1929 // ((X1 ^ X2) || (X3 ^ X4)) != 0 --> (X1 != X2) || (X3 != X4)
1931 Value *Cmp34 = Builder.CreateICmp(Pred, X3, X4);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp418 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
/freebsd-12-stable/sys/ofed/include/rdma/
H A Dib_verbs.h1667 IB_IPV4_MORE_FRAG = 0X4 /* For All fragmented packets except the
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3782 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4197 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4620 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5880 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6612 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6904 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
15347 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;

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