/freebsd-12-stable/sys/contrib/libsodium/src/libsodium/crypto_pwhash/scryptsalsa208sha256/sse/ |
H A D | pwhash_scryptsalsa208sha256_sse.c | 67 ARX(X1, X0, X3, 7) \ 68 ARX(X2, X1, X0, 9) \ 70 ARX(X0, X3, X2, 18) \ 78 ARX(X3, X0, X1, 7) \ 79 ARX(X2, X3, X0, 9) \ 81 ARX(X0, X1, X2, 18) \ 89 * Apply the salsa20/8 core to the block provided in (X0 ... X3) ^ (Z0 ... Z3). 93 __m128i Y0 = X0 = _mm_xor_si128(X0, (in)[0]); \ 100 SALSA20_2ROUNDS(out)[0] = X0 114 __m128i X0, X1, X2, X3; local 166 __m128i X0, X1, X2, X3; local [all...] |
/freebsd-12-stable/contrib/libstdc++/include/ext/ |
H A D | typelist.h | 313 #define _GLIBCXX_TYPELIST_CHAIN1(X0) __gnu_cxx::typelist::chain<X0, __gnu_cxx::typelist::null_type> 314 #define _GLIBCXX_TYPELIST_CHAIN2(X0, X1) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN1(X1) > 315 #define _GLIBCXX_TYPELIST_CHAIN3(X0, X1, X2) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN2(X1, X2) > 316 #define _GLIBCXX_TYPELIST_CHAIN4(X0, X1, X2, X3) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN3(X1, X2, X3) > 317 #define _GLIBCXX_TYPELIST_CHAIN5(X0, X1, X2, X3, X4) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN [all...] |
/freebsd-12-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha256-c64xplus.pl | 43 ($Xn,$X0,$K)=("B7","B8","B9"); 118 || SWAP4 $Xn,$X0 122 || SWAP2 $X0,$X0 139 ADD $X0,$T1,$T1 ; T1 += X[i]; 140 || STW $X0,*$Xib++ 151 || MV $X0,$X14 152 || SWAP4 $Xn,$X0 153 SWAP2 $X0,$X0 [all...] |
H A D | sha1-c64xplus.pl | 41 ($X0,$X2,$X8,$X13) = ("A26","B26","A27","B27"); 138 || LDW *${XPA}++,$X0 ; fetches from X ring buffer are 163 || XOR $X0,$X2,$TX0 ; Xupdate XORs are 1 iteration ahead 164 || LDW *${XPA}++,$X0 194 || XOR $X0,$X2,$TX0 195 || LDW *${XPA}++,$X0 231 || XOR $X0,$X2,$TX0 232 || LDW *${XPA}++,$X0 271 || XOR $X0,$X2,$TX0 272 || LDW *${XPA}++,$X0 [all...] |
/freebsd-12-stable/contrib/binutils/opcodes/ |
H A D | ia64-opc-x.c | 25 #define X0 IA64_TYPE_X, 0 macro 65 {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, 66 {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, 67 {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, 70 X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL 79 X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL 81 X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL 163 #undef X0 macro
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.cpp | 29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); 79 markSuperRegs(Reserved, RISCV::X0); // zero 99 return PhysReg == RISCV::X0;
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H A D | RISCVAsmPrinter.cpp | 106 OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
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H A D | RISCVISelDAGToDAG.cpp | 72 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); 80 // Only the first instruction has X0 as its source. 118 RISCV::X0, XLenVT);
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H A D | RISCVExpandPseudoInsts.cpp | 269 .addReg(RISCV::X0) 354 .addReg(RISCV::X0) 513 .addReg(RISCV::X0) 578 .addReg(RISCV::X0) 609 .addReg(RISCV::X0)
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H A D | RISCVInstrInfo.cpp | 171 Register SrcReg = RISCV::X0; 198 // Only the first instruction has X0 as its source. 500 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0); 782 .addReg(RISCV::X0, RegState::Define)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 105 TII->get(TargetOpcode::COPY), AArch64::X0) 124 // Insert a copy from X0 to TLSBaseAddrReg for later. 128 .addReg(AArch64::X0);
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H A D | AArch64CollectLOH.cpp | 261 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs"); 263 if (AArch64::X0 <= Reg && Reg <= AArch64::X28) 264 return Reg - AArch64::X0;
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H A D | AArch64AsmPrinter.cpp | 284 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack 291 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack 322 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" + 473 .addReg(AArch64::X0) 485 if (Reg != AArch64::X0) 487 .addReg(AArch64::X0) 1128 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); 1135 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); [all...] |
H A D | AArch64CallingConvention.cpp | 23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
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/freebsd-12-stable/sys/crypto/skein/ |
H A D | skein_block.c | 83 u64b_t X0,X1,X2,X3; /* local copy of context vars, for speed */ local 87 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; 109 X0 = w[0] + ks[0]; /* do the first full key injection */ 130 X0 += ks[((R)+1) % 5]; /* inject the key schedule value */ \ 141 X0 += ks[r+(R)+0]; /* inject the key schedule value */ \ 215 ctx->X[0] = X0 ^ w[0]; 268 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ local 272 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; 301 X0 = w[0] + ks[0]; /* do the first full key injection */ 326 X0 [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVAsmBackend.cpp | 87 // c.beqz $rs1, $imm -> beq $rs1, X0, $imm. 90 Res.addOperand(MCOperand::createReg(RISCV::X0)); 94 // c.bnez $rs1, $imm -> bne $rs1, X0, $imm. 97 Res.addOperand(MCOperand::createReg(RISCV::X0)); 101 // c.j $imm -> jal X0, $imm. 103 Res.addOperand(MCOperand::createReg(RISCV::X0));
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H A D | RISCVMCCodeEmitter.cpp | 129 // Emit JALR X0, X6, 0 130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
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/freebsd-12-stable/sys/contrib/libsodium/src/libsodium/crypto_aead/aes256gcm/aesni/ |
H A D | aead_aes256gcm_aesni.c | 62 __m128i X0, X1, X2, X3; local 65 X0 = _mm_loadu_si128((const __m128i *) &key[0]); 66 rkeys[i++] = X0; 73 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x10)); \ 74 X0 = _mm_xor_si128(X0, X3); \ 75 X3 = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(X3), _mm_castsi128_ps(X0), 0x8c)); \ 76 X0 = _mm_xor_si128(_mm_xor_si128(X0, X3), X1); \ 77 rkeys[i++] = X0; \ [all...] |
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_mips.cpp | 114 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
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H A D | xray_mips64.cpp | 123 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCAsmPrinter.cpp | 1216 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1217 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0)); 1223 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0)); 1302 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1303 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0)); 1309 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 31 case AArch64::X0: return AArch64::W0; 71 case AArch64::W0: return AArch64::X0;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 71 Register Reg = RISCV::X0 + RegNo;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 97 {codeview::RegisterId::ARM64_X0, AArch64::X0},
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 1647 Register SrcReg = RISCV::X0; 1658 // Only the first instruction has X0 as its source. 1808 .addReg(RISCV::X0)
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