Searched refs:WR4 (Results 1 - 25 of 60) sorted by relevance

123

/freebsd-12-stable/sys/arm/freescale/imx/
H A Dimx6_ccm.c75 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) function
97 WR4(sc, CCM_CCGR0, reg);
102 WR4(sc, CCM_CCGR1, reg);
109 WR4(sc, CCM_CCGR2, reg);
114 WR4(sc, CCM_CCGR3, reg);
119 WR4(sc, CCM_CCGR4, reg);
124 WR4(sc, CCM_CCGR5, reg);
129 WR4(sc, CCM_CCGR6, reg);
181 WR4(sc, CCM_CGPR, reg);
184 WR4(s
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H A Dimx_epit.c142 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value) function
203 WR4(sc, EPIT_LR, 0xffffffff);
204 WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
234 WR4(sc, EPIT_CR, sc->ctlreg);
235 WR4(sc, EPIT_SR, EPIT_SR_OCIF);
247 WR4(sc, EPIT_LR, ticks);
261 WR4(sc, EPIT_CR, sc->ctlreg);
286 WR4(sc, EPIT_CR, sc->ctlreg);
450 WR4(sc, EPIT_CR, 0);
H A Dimx6_snvs.c89 WR4(struct snvs_softc *sc, bus_size_t offset, uint32_t value) function
104 WR4(sc, SNVS_LPCR, sc->lpcr);
163 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32)));
164 WR4(sc, SNVS_LPSRTCLR, (uint32_t)(sbt >> (SBT_LSB)));
H A Dimx_iomux.c113 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) function
142 WR4(sc, reg, val);
164 WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
167 WR4(sc, cfg->padconf_reg, cfg->padconf_val);
288 WR4(iomux_sc, regaddr, val);
305 WR4(iomux_sc, regaddr, val);
/freebsd-12-stable/sys/arm/nvidia/drm2/
H A Dtegra_dc.c58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
429 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val);
432 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y));
433 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h));
434 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size));
437 WR4(sc, DC_WIN_DDA_INCREMENT,
439 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda);
440 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda);
443 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]);
445 WR4(s
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H A Dtegra_hdmi.c61 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
359 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
361 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW,
363 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,
365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW,
367 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH,
370 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL,
391 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
393 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW,
395 WR4(s
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/freebsd-12-stable/sys/dev/ffec/
H A Dif_ffec.c232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) function
325 WR4(sc, FEC_IER_REG, FEC_IER_MII);
327 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
349 WR4(sc, FEC_IER_REG, FEC_IER_MII);
351 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
437 WR4(sc, FEC_RCR_REG, rcr);
438 WR4(sc, FEC_TCR_REG, tcr);
439 WR4(sc, FEC_ECR_REG, ecr);
491 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
492 WR4(s
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/freebsd-12-stable/sys/arm/xilinx/
H A Duart_dev_cdnc.c61 #define WR4(bas, reg, value) \ macro
214 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
215 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
262 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
275 WR4(bas, CDNC_UART_CTRL_REG,
279 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
280 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
283 WR4(bas, CDNC_UART_MODEM_STAT_REG,
288 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
289 WR4(ba
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H A Dzy7_slcr.c79 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
118 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
126 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
140 WR4(sc, ZY7_SLCR_REBOOT_STAT,
144 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
167 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
170 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
198 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
201 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
243 WR4(s
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H A Dzy7_devcfg.c102 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
405 WR4(sc, ZY7_DEVCFG_CTRL,
418 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
434 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
435 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
439 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
448 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
459 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
471 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
472 WR4(s
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H A Dzy7_gpio.c98 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro
208 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
212 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
216 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
221 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
223 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
243 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
247 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
279 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
/freebsd-12-stable/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c248 WR4(struct bcm_sdhost_softc *sc, bus_size_t off, uint32_t val) function
284 WR4(sc, off & ~3, val32);
295 WR4(sc, off & ~3, val32);
353 WR4(sc, HC_POWER, 0);
355 WR4(sc, HC_COMMAND, 0);
356 WR4(sc, HC_ARGUMENT, 0);
357 WR4(sc, HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT);
358 WR4(sc, HC_CLOCKDIVISOR, 0);
359 WR4(sc, HC_HOSTSTATUS, HC_HSTST_RESET);
360 WR4(s
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/freebsd-12-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c423 WR4(sc, sc->base_reg, reg);
436 WR4(sc, sc->base_reg, reg);
574 WR4(sc, sc->base_reg, reg);
579 WR4(sc, PLLE_AUX, reg);
589 WR4(sc, sc->misc_reg, reg);
594 WR4(sc, PLLE_SS_CNTL, reg);
600 WR4(sc, sc->base_reg, reg);
613 WR4(sc, PLLE_SS_CNTL, reg);
616 WR4(sc, PLLE_SS_CNTL, reg);
620 WR4(s
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H A Dtegra124_xusbpadctl.c177 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
383 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
392 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
394 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
409 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
423 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
430 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
435 WR4(s
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/freebsd-12-stable/sys/arm64/rockchip/
H A Drk_tsadc.c90 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
417 WR4(sc, TSADC_INT_EN, val);
421 WR4(sc, TSADC_COMP_SHUT(sensor->channel), val);
424 WR4(sc, TSADC_AUTO_CON, val);
428 WR4(sc, TSADC_COMP_INT(sensor->channel), val);
431 WR4(sc, TSADC_INT_EN, val);
447 WR4(sc, TSADC_AUTO_CON, val);
451 WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */
452 WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */
453 WR4(s
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H A Drk_pcie_phy.c104 #define WR4(sc, reg, mask, val) \ macro
114 WR4(sc, GRF_SOC_CON8, 0x7FF,
120 WR4(sc, GRF_SOC_CON8, 1, 1);
123 WR4(sc, GRF_SOC_CON8, 1, 0);
133 WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);
162 WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0);
225 WR4(sc, GRF_SOC_CON_5_PCIE,
/freebsd-12-stable/sys/arm/nvidia/
H A Dtegra_rtc.c77 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
157 WR4(sc, RTC_SECONDS, tv.tv_sec);
173 WR4(sc, RTC_INTR_STATUS, status);
233 WR4(sc, RTC_SECONDS_ALARM0, 0);
234 WR4(sc, RTC_SECONDS_ALARM1, 0);
235 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF);
236 WR4(sc, RTC_INTR_MASK, 0);
H A Dtegra_i2c.c193 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
245 WR4(sc, I2C_FIFO_CONTROL, reg);
273 WR4(sc, I2C_CLK_DIVISOR,
284 WR4(sc, I2C_BUS_CLEAR_CONFIG,
289 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
299 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);
333 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
334 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
335 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
340 WR4(s
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H A Dtegra_mc.c99 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
149 WR4(sc, MC_INTSTATUS, stat);
183 WR4(sc, MC_INTSTATUS, stat);
191 WR4(sc, MC_INTMASK, 0);
192 WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK);
262 WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
H A Dtegra_usbphy.c315 #define WR4(sc, offs, val) \ macro
342 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
362 WR4(sc, IF_USB_SUSP_CTRL, val);
367 WR4(sc, UTMIP_TX_CFG0, val);
374 WR4(sc, UTMIP_HSRX_CFG0, val);
379 WR4(sc, UTMIP_HSRX_CFG1, val);
384 WR4(sc, UTMIP_DEBOUNCE_CFG0, val);
388 WR4(sc, UTMIP_MISC_CFG0, val);
394 WR4(sc, IF_USB_SUSP_CTRL, val);
398 WR4(s
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/freebsd-12-stable/sys/riscv/riscv/
H A Dplic.c105 #define WR4(sc, reg, val) \ macro
176 WR4(sc, PLIC_CLAIM(sc, cpu), pending);
191 WR4(sc, PLIC_PRIORITY(src->irq), 0);
203 WR4(sc, PLIC_PRIORITY(src->irq), 1);
300 WR4(sc, PLIC_PRIORITY(irq), 0);
365 WR4(sc, PLIC_THRESHOLD(sc, cpu), 0);
423 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
440 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
/freebsd-12-stable/sys/dev/cadence/
H A Dif_cgem.c203 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
267 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
269 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
272 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
273 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
358 WR4(sc, CGEM_HASH_TOP, hash_hi);
359 WR4(sc, CGEM_HASH_BOT, hash_lo);
360 WR4(sc, CGEM_NET_CFG, net_cfg);
817 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
924 WR4(s
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/freebsd-12-stable/sys/dev/sdhci/
H A Dfsl_sdhci.c199 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) function
402 WR4(sc, SDHC_PROT_CTRL, val32);
420 WR4(sc, off & ~3, val32);
460 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
461 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
480 WR4(sc, USDHC_MIX_CONTROL, val32);
491 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
499 WR4(sc, off & ~3, val32);
512 WR4(sc, off, val);
596 WR4(s
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/freebsd-12-stable/sys/arm/allwinner/
H A Daw_thermal.c380 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) macro
407 WR4(sc, THS_CALIB0, calib[0]);
409 WR4(sc, THS_CALIB1, calib[1]);
412 WR4(sc, THS_CTRL1, ADC_CALI_EN);
413 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
414 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
417 WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT);
420 WR4(sc, THS_FILTER, sc->conf->filter);
423 WR4(sc, THS_INTS, RD4(sc, THS_INTS));
424 WR4(s
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/freebsd-12-stable/sys/arm/mv/
H A Dmv_thermal.c128 #define WR4(sc, reg, val) \ macro
170 WR4(sc, CONTROL0, reg);
186 WR4(sc, CONTROL0, reg);
192 WR4(sc, CONTROL0, reg);
233 WR4(sc, CONTROL0, reg);
249 WR4(sc, CONTROL1, reg);
254 WR4(sc, CONTROL0, reg);

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