Searched refs:TargetSU (Results 1 - 4 of 4) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ScheduleDAG.cpp | 599 const SUnit &TargetSU,
603 int UpperBound = Node2Index[TargetSU.NodeNum];
649 // Starting from TargetSU, visit all predecessors up
652 WorkList.push_back(&TargetSU);
704 bool ScheduleDAGTopologicalSort::WillCreateCycle(SUnit *TargetSU, SUnit *SU) {
706 // Is SU reachable from TargetSU via successor edges?
707 if (IsReachable(SU, TargetSU))
709 for (const SDep &PredDep : TargetSU->Preds)
717 const SUnit *TargetSU) {
719 // If insertion of the edge SU->TargetSU woul
[all...] |
| H A D | MachinePipeliner.cpp | 1130 SUnit *TargetSU = D.getSUnit(); local
1136 TargetSU->addPred(Dep);
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAG.h | 731 /// subtree of StartSU and in the predecessor subtree of TargetSU.
732 /// StartSU and TargetSU are not in the array.
733 /// Success is false if TargetSU is not in the successor subtree of
735 std::vector<int> GetSubGraph(const SUnit &StartSU, const SUnit &TargetSU,
738 /// Checks if \p SU is reachable from \p TargetSU.
739 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
741 /// Returns true if addPred(TargetSU, SU) creates a cycle.
742 bool WillCreateCycle(SUnit *TargetSU, SUnit *SU);
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 211 /// IsReachable - Checks if SU is reachable from TargetSU.
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
213 return Topo.IsReachable(SU, TargetSU);
216 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
219 return Topo.WillCreateCycle(SU, TargetSU);
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